Optimization of clock gating logic for low power LSI design
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Author
Bibliographic Information
- Title
-
Optimization of clock gating logic for low power LSI design
- Author
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満, 欣
- Author(Another name)
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マン, シン
- University
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早稲田大学
- Types of degree
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博士(工学)
- Grant ID
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甲第3740号
- Degree year
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2012-09-15
Note and Description
博士論文