An implicit enumeration algorithm to generate tests generation algorithms

An implicit enumeration algorithm to generate tests generation algorithms

- GOEL P.

Cited by (54)

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Author(s)

- GOEL P.

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IEEE Trans. Comput.

IEEE Trans. Comput. C-30(3), 215-222, 1981

Cited by: 54

1

A Practical Threshold Test Generation for Error Tolerant Application

ICHIHARA Hideyuki , SUTOH Kenta , YOSHIKAWA Yuki , INOUE Tomoo

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Concurrent Generation of lrredundant Combinational Circuits and Minimal Test Sets [in Japanese]

KAJIHARA Seiji , KINOSHITA Kozo

IPSJ Journal 36(6), 1495-1501, 1995-06-15

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On Evaluation of Fault Parallelism for a Parallel Sequential Test Generation System DESCARTES Based on Real-Valued Logic Simulation [in Japanese]

DATE Hiroshi , NAKAO Michinobu , HATAYAMA Kazumi

The Transactions of the Institute of Electronics,Information and Communication Engineers. A 00079(00001), 47-56, 1996-01-25

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Optimization of Neighborhood Size for Parallel Local Search and Its Application to Test Generation of Combinational Circuits [in Japanese]

NATSUME Koichiro , HATAYAMA Kazumi , DATE Hiroshi

Transactions of Information Processing Society of Japan 37(6), 1187-1195, 1996-06-15

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On Invaliant Implication Relataions for Removing Partial Circuits [in Japanese]

ICHIHARA Hideyuki , KAJIHARA Seiji , KINOSHITA Kozo

The Transactions of the Institute of Electronics,Information and Communication Engineers. 00079(00012), 1037-1045, 1996-12-25

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6

Redundancy Identification for Combinational Circuits [in Japanese]

MINAMIYAMA Tetsuro , TAKAMATSU Yuzo

The Transactions of the Institute of Electronics,Information and Communication Engineers. 00080(00005), 456-459, 1997-05-25

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Current Testing of Open Faults in TTL Combinational Circuits on Printed Circuit Boards [in Japanese]

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Journal of Japan Institute of Electronics Packaging 1(4), 284-293, 1998-09-01

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8

A Method of Search Space Pruning Based on Search State Dominance [in Japanese]

FUJINO Takayuki , FUJIWARA Hideo

The Transactions of the Institute of Electronics,Information and Communication Engineers. 76(5), 218-227, 1993-05-25

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An Optimal Scheme of Parallel Processing for Test Generation in a Distributed System [in Japanese]

INOUE Tomoo , YONEZAWA Tomonori , FUJIWARA Hideo

The Transactions of the Institute of Electronics,Information and Communication Engineers. 76(11), 604-612, 1993-11-25

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10

Test Pattern Generation for Crosstalk Faults Considering the Gate Delay [in Japanese]

ITAZAKI Noriyoshi , NAITOH Hisao , KINOSHITA Kozo

The Transactions of the Institute of Electronics,Information and Communication Engineers. 77(5), 384-391, 1994-05-25

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Test Generation for Sequential Circuits Using Parallel Fault Simulation with Random Inputs [in Japanese]

TAKAMATSU Yuzo , KODAMA Tsuyoshi , HIGASHI Isao

The Transactions of the Institute of Electronics,Information and Communication Engineers. 77(12), 803-811, 1994-12-25

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VLSI Testing. [in Japanese]

FUJIWARA Hideo

The Journal of the Institute of Electronics,Information and Communication Engineers 77(3), 288-295, 1994-03-25

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13

On the Effect of Scheduling in Test Generation

INOUE Tomoo , MAEDA Hironori , FUJIWARA Hideo

IEICE TRANSACTIONS on Information and Systems 79(8), 1190-1197, 1996-08-25

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14

A Note on a testability metric for redundant logic circuits [in Japanese]

DOI Masato , TAKAHASHI Ryuichi

IEICE technical report. Computer systems 104(12), 27-32, 2004-04-09

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15

A Note on a testability metric for redundant logic circuits [in Japanese]

DOI Masato , TAKAHASHI Ryuichi

IEICE technical report. Dependable computing 104(13), 27-32, 2004-04-09

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16

SPIRIT : A High Robust Combinational Test Generation Algorithm

GIZDARSKI Emil , FUJIWARA Hideo

Technical report of IEICE. ICD 100(474), 209-214, 2000-11-30

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17

Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation

NAMBA Kazuteru , ITO Hideo

IEICE transactions on information and systems 88(9), 2135-2142, 2005-09-01

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18

A Constrained Test Generation Method for Low Power Testing [in Japanese]

TOUNOUE Yoshiaki , WEN Xiaoqing , KAJIHARA Seiji , MIYASE Kohei , SUZUKI Tatsuya , YAMATO Yuta

IEICE technical report 106(467), 109-114, 2007-01-11

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19

A Constrained Test Generation Method for Low Power Testing [in Japanese]

TOUNOUE Yoshiaki , WEN Xiaoqing , KAJIHARA Seiji , MIYASE Kohei , SUZUKI Tatsuya , YAMATO Yuta

IEICE technical report 106(468), 109-114, 2007-01-11

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20

A Transition Delay Test Generation Method for Capture Power Reduction during At-Speed Scan Testing [in Japanese]

FUKUZAWA Tomoaki , MIYASE Kohei , YAMATO Yuta , FURUKAWA Hiroshi , WEN Xiaoqing , KAJIHARA Seiji

IEICE technical report 107(337), 7-12, 2007-11-13

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21

A Transition Delay Test Generation Method for Capture Power Reduction during At-Speed Scan Testing [in Japanese]

FUKUZAWA Tomoaki , MIYASE Kohei , YAMATO Yuta , FURUKAWA Hiroshi , WEN Xiaoqing , KAJIHARA Seiji

IEICE technical report 107(334), 7-12, 2007-11-13

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22

A Transition Delay Test Generation Method for Capture Power Reduction during At-Speed Scan Testing [in Japanese]

FUKUZAWA Tomoaki , MIYASE Kohei , YAMATO Yuta , FURUKAWA Hiroshi , WEN Xiaoqing , KAJIHARA Seiji

情報処理学会研究報告. SLDM, [システムLSI設計技術] 132, 7-12, 2007-11-20

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23

Optimization of neighborhood size for parallel local search and its application to test generation of combinational circuits [in Japanese]

NATSUME Koichiro , HATAYAMA Kazumi , DATE Hiroshi

IPSJ SIG Notes 1, 65-73, 1995-05-18

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24

On Invariant Implication Relations in Redundancy Removal for Combinational Circuits [in Japanese]

KAJIHARA Seiji , ICHIHARA Hideyuki , KINOSHITA Kozo

Technical report of IEICE. VLD 95(307), 23-29, 1995-10-20

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25

Toward a Testability Measurement Model Based on Real-Valued Logic Simulation [in Japanese]

DATE Hiroshi , YASUURA Hiroto

Technical report of IEICE. VLD 96(299), 71-75, 1996-10-18

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26

SPIRIT : A High Robust Combinational Test Generation Algorithm

GIZDARSKI Emil , FUJIWARA Hideo

Technical report of IEICE. VLD 100(473), 209-214, 2000-11-23

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27

Optimal seed decision for deterministic delay fault detection BIST [in Japanese]

SUZUKI Kazuki , ITO Hideo

Technical report of IEICE. VLD 101(467), 37-42, 2001-11-22

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28

On Efficient Identification and Preservation of Indirect Implications in Static Learning [in Japanese]

SARUWATARI Keitaro , KAJIHARA Seiji

Technical report of IEICE. VLD 102(476), 25-28, 2002-11-21

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29

Optimal Granularity of Parallel Test Generation on the Client -Agent- Server Model

Tomoo Inoue , Tomonori Yonezawa , Hideo Fujiwara

IPSJ Journal 35(8), 1614-1623, 1994-08-15

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30

On Efficient Identification and Preservation of Indirect Implications in Static Learning [in Japanese]

SARUWATARI Keitaro , KAJIHARA Seiji

Technical report of IEICE. ICD 102(477), 25-28, 2002-11-21

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31

Comparison of exact solutions and greedy solutions in static test compaction [in Japanese]

YAGISAWA Kei , YAMAZAKI Koji , HOSOKAWA Toshinori , TAMAKI Hisao

IEICE technical report 107(482), 77-82, 2008-02-08

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32

A Test Generation Model for Threshold Testing [in Japanese]

SUTOH Kenta , YOSHIKAWA Yuki , ICHIHARA Hideyuki , INOUE Tomoo

IEICE technical report 108(352), 5-10, 2008-12-05

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33

A Test Generation Algorithm Based on 5-valued Logic for Threshold Testing [in Japanese]

IZUMI Nobukazu , YOSHIKAWA Yuki , ICHIHARA Hideyuki , INOUE Tomoo

IEICE technical report 109(95), 13-18, 2009-06-12

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34

A Novel ATPG Method for Capture Power Reduction during Scan Testing

WEN Xiaoqing , KAJIHARA Seiji , MIYASE Kohei , SUZUKI Tatsuya , SALUJA Kewal K. , WANG Laung-Terng , KINOSHITA Kozo

IEICE Transactions on Information and Systems 90(9), 1398-1405, 2007-09-01

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35

A Method for Forward Test Generation of Sequential Circuits [in Japanese]

TAKAMATSU Yuzo , OGAWA Taijiro , TAKAHASHI Hiroshi

The Transactions of the Institute of Electronics,Information and Communication Engineers. 75(9), 864-873, 1992-09-25

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36

Sequential Circuit Test Generation by Real Number Simulation [in Japanese]

HIKONE Kazunori , IKEDA Mitsuji , HATAYAMA Kazumi , HAYASHI Terumine

The Transactions of the Institute of Electronics,Information and Communication Engineers. 75(11), 1089-1098, 1992-11-25

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37

Removal of Redundancy in Combinational Circuits by Classification of Undetectable Faults [in Japanese]

KAJIHARA Seiji , SHIBA Haruko , KINOSHITA Kozo

The Transactions of the Institute of Electronics,Information and Communication Engineers. 75(2), 107-115, 1992-02-25

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38

Test Generation for Sequential Circuits Using State Transition Diagram and Test Generarion for Combinational Circuit Part [in Japanese]

HASEGAWA Tetsu , MIURA Kyoko , OHMAMEUDA Toshiaki , ITO Hideo

The Transactions of the Institute of Electronics,Information and Communication Engineers. 00083(00003), 339-347, 2000-03-25

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39

A Study for Testability of Redundant Faults in Combinational Circuits Using Delay Effects

YU Xiangqiu , TAKAHASHI Hiroshi , TAKAMATSU Yuzo

IEICE transactions on information and systems 78(7), 822-829, 1995-07-25

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40

Very Fast Fault Simulation for Voltage Stuck-at Faults in Analog/Digital Mixed Circuit

TESHIMA Shigeharu , CHUJO Naoya , TERASHIMA Ryuta

IEICE transactions on information and systems 78(7), 853-860, 1995-07-25

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41

Test Generation Algorithms (<Special Issue> VLSI-CAD and Artificial Intelligence) [in Japanese]

FUJIWARA Hideo , Hideo Fujiwara

Journal of the Japanese Society for Artificial Intelligence 8(2), 166-172, 1993-03-01

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42

Test Generation for Sequential Circuits Based on Boolean Function Manipulation [in Japanese]

CHOI Hoyong , KOHARA Takashi , ISHIURA Nagisa , SHIRAKAWA Isao , MOTOHARA Akira

The Transactions of the Institute of Electronics,Information and Communication Engineers. A 76(6), 835-843, 1993-06-25

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43

Average Power Reduction in Scan Testing by Test Vector Modification

KAJIHARA Seiji , ISHIDA Koji , MIYASE Kohei

IEICE Trans. Info. and Syst., D 85(10), 1483-1489, 2002-10-01

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44

Test Cost Reduction for Logic Circuits : Reduction of Test Data Volume and Test Application Time [in Japanese]

HIGAMI Yoshinobu , KAJIHARA Seiji , ICHIHARA Hideyuki , TAKAMATSU Yuzo

The Transactions of the Institute of Electronics,Information and Communication Engineers. 87(3), 291-307, 2004-03-01

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45

Acceleration of Test Generation for Sequential Circuit Using Knowledge Obtained from Synthesis for Testability [in Japanese]

NAKAZATO Masato , OHTAKE Satoshi , FUJIWARA Hideo

IEICE technical report. Dependable computing 104(664), 33-38, 2005-02-18

References (9) Cited by (2)
46

Analysis of Effective Decision Nodes on Test Generation [in Japanese]

OMORI Yusho , HOSOKAWA Toshinori , YOSHIMURA Masayoshi , YAMAZAKI Kouji

IEICE technical report 106(528), 37-42, 2007-02-02

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47

UIO Sequence and Test Generation for Sequential Circuits Using Extra Outputs [in Japanese]

UCHIYAMA Keisuke , OHMAMEUDA Toshiaki , ITO Hideo

情報処理学会研究報告. SLDM, [システムLSI設計技術] 95, 47-54, 2000-02-09

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48

Optimal seed decision for deterministic delay fault detection BIST [in Japanese]

SUZUKI Kazuki , ITO Hideo

Technical report of IEICE. ICD 101(470), 37-42, 2001-11-22

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49

On Efficient Identification and Preservation of Indirect Implications in Static Learning [in Japanese]

SARUWATARI Keitaro , KAJIHARA Seiji

IEICE technical report. Dependable computing 102(479), 25-28, 2002-11-21

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50

A Method for Fast Identification of Unnecessary-to-Test Paths for Delay Faults in Logic Circuits [in Japanese]

KAJIHARA Seiji , KINOSHITA Kozo , POMERANZ Irith , REDDY Sudhakar M.

The Transactions of the Institute of Electronics,Information and Communication Engineers. 00082(00007), 888-895, 1999-07

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51

Test Generation of Combinational Circuits by the Hopfield [in Japanese]

HORITA Tadayoshi , TAKANAMI Itsuo , WATANABE Takahiro

The Transactions of the Institute of Electronics,Information and Communication Engineers. A 00078(00009), 1217-1220, 1995-09-25

References (7)
52

A Study for Identification of Redundant Faults in Combinational Circuits [in Japanese]

MINAMIYAMA Tetsuro , TAKAMATSU Yuzo

The Transactions of the Institute of Electronics,Information and Communication Engineers. 00081(00010), 1149-1156, 1998-10

References (20) Cited by (1)
53

A Fault Model and Test Generation for Bridging Faults in CMOS Circuits [in Japanese]

TAKAMATSU Yuzo , SHIOSAKA Tomoko , YAMADA Teruhiko , YAMAZAKI Koji

The Transactions of the Institute of Electronics,Information and Communication Engineers. 00081(00006), 872-879, 1998-06

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54

Solving Satisfiability Problems Using Reconfigurable Hardware [in Japanese]

SUYAMA Takayuki , YOKOO Makoto , SAWADA Hiroshi , NAGOYA Akira

The Transactions of the Institute of Electronics,Information and Communication Engineers. 00084(00004), 410-420, 2001-04-01

References (23) Cited by (2)

An implicit enumeration algorithm to generate tests generation algorithms

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