On the Acceleration of Test Generation Algorithms

On the Acceleration of Test Generation Algorithms

- FUJIWARA H.

Cited by (43)

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Author(s)

- FUJIWARA H.

Journal

IEEE Trans. Computers

IEEE Trans. Computers C-33(12), 1137-1144, 1983

Cited by: 43

1

Concurrent Generation of lrredundant Combinational Circuits and Minimal Test Sets [in Japanese]

KAJIHARA Seiji , KINOSHITA Kozo

IPSJ Journal 36(6), 1495-1501, 1995-06-15

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2

Evaluation of the Maximum Number of Switching Gates for CMOS Circuits [in Japanese]

UEDA Hiroaki , KINOSHITA Kozo

The Transactions of the Institute of Electronics,Information and Communication Engineers. 00078(00003), 367-375, 1995-03-25

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3

On Invaliant Implication Relataions for Removing Partial Circuits [in Japanese]

ICHIHARA Hideyuki , KAJIHARA Seiji , KINOSHITA Kozo

The Transactions of the Institute of Electronics,Information and Communication Engineers. 00079(00012), 1037-1045, 1996-12-25

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4

IDDQ Test Vector Selection for Transistor Short Fault Testing [in Japanese]

WEN Xiaoqing , TAMAMOTO Hideo , KINOSHITA Kozo

The Transactions of the Institute of Electronics,Information and Communication Engineers. 00079(00012), 1113-1122, 1996-12-25

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5

A Simulation-Based Diagnosis of Logical Faults in Combinational Circuits [in Japanese]

YAMADA Teruhiko , YAMAZAKI Koji

The Transactions of the Institute of Electronics,Information and Communication Engineers. 00079(00012), 1123-1130, 1996-12-25

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6

Redundancy Identification for Combinational Circuits [in Japanese]

MINAMIYAMA Tetsuro , TAKAMATSU Yuzo

The Transactions of the Institute of Electronics,Information and Communication Engineers. 00080(00005), 456-459, 1997-05-25

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7

A Method of Search Space Pruning Based on Search State Dominance [in Japanese]

FUJINO Takayuki , FUJIWARA Hideo

The Transactions of the Institute of Electronics,Information and Communication Engineers. 76(5), 218-227, 1993-05-25

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8

An Optimal Scheme of Parallel Processing for Test Generation in a Distributed System [in Japanese]

INOUE Tomoo , YONEZAWA Tomonori , FUJIWARA Hideo

The Transactions of the Institute of Electronics,Information and Communication Engineers. 76(11), 604-612, 1993-11-25

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9

A Method of Diagnosing Bridging Faults between n Nets in Combinational Circuits [in Japanese]

YAMAZAKI Koji , YAMADA Teruhiko

The Transactions of the Institute of Electronics,Information and Communication Engineers. 77(1), 77-85, 1994-01-25

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10

Test Generation for Sequential Circuits Using Parallel Fault Simulation with Random Inputs [in Japanese]

TAKAMATSU Yuzo , KODAMA Tsuyoshi , HIGASHI Isao

The Transactions of the Institute of Electronics,Information and Communication Engineers. 77(12), 803-811, 1994-12-25

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11

VLSI Testing. [in Japanese]

FUJIWARA Hideo

The Journal of the Institute of Electronics,Information and Communication Engineers 77(3), 288-295, 1994-03-25

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12

On the Effect of Scheduling in Test Generation

INOUE Tomoo , MAEDA Hironori , FUJIWARA Hideo

IEICE TRANSACTIONS on Information and Systems 79(8), 1190-1197, 1996-08-25

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13

Performance Analysis of Parallel Test Generation for Combinational Circuits

INOUE Tomoo , FUJII Takaharu , FUJIWARA Hideo

IEICE TRANSACTIONS on Information and Systems 79(9), 1257-1265, 1996-09-25

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14

SPIRIT : A High Robust Combinational Test Generation Algorithm

GIZDARSKI Emil , FUJIWARA Hideo

Technical report of IEICE. ICD 100(474), 209-214, 2000-11-30

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15

On Invariant Implication Relations in Redundancy Removal for Combinational Circuits [in Japanese]

KAJIHARA Seiji , ICHIHARA Hideyuki , KINOSHITA Kozo

Technical report of IEICE. VLD 95(307), 23-29, 1995-10-20

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16

SPIRIT : A High Robust Combinational Test Generation Algorithm

GIZDARSKI Emil , FUJIWARA Hideo

Technical report of IEICE. VLD 100(473), 209-214, 2000-11-23

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17

On Efficient Identification and Preservation of Indirect Implications in Static Learning [in Japanese]

SARUWATARI Keitaro , KAJIHARA Seiji

Technical report of IEICE. VLD 102(476), 25-28, 2002-11-21

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18

Optimal Granularity of Parallel Test Generation on the Client -Agent- Server Model

Tomoo Inoue , Tomonori Yonezawa , Hideo Fujiwara

IPSJ Journal 35(8), 1614-1623, 1994-08-15

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19

On Efficient Identification and Preservation of Indirect Implications in Static Learning [in Japanese]

SARUWATARI Keitaro , KAJIHARA Seiji

Technical report of IEICE. ICD 102(477), 25-28, 2002-11-21

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20

Comparison of exact solutions and greedy solutions in static test compaction [in Japanese]

YAGISAWA Kei , YAMAZAKI Koji , HOSOKAWA Toshinori , TAMAKI Hisao

IEICE technical report 107(482), 77-82, 2008-02-08

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21

An n-Detection Test Generation Method to Increase Fault Sensitization Coverage [in Japanese]

HOSOKAWA Toshinori , YAMAZAKI Koji

The IEICE transactions on information and systems 90(6), 1474-1482, 2007-06-01

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22

A Method for Forward Test Generation of Sequential Circuits [in Japanese]

TAKAMATSU Yuzo , OGAWA Taijiro , TAKAHASHI Hiroshi

The Transactions of the Institute of Electronics,Information and Communication Engineers. 75(9), 864-873, 1992-09-25

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23

Removal of Redundancy in Combinational Circuits by Classification of Undetectable Faults [in Japanese]

KAJIHARA Seiji , SHIBA Haruko , KINOSHITA Kozo

The Transactions of the Institute of Electronics,Information and Communication Engineers. 75(2), 107-115, 1992-02-25

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24

Test Generation for Sequential Circuits Using State Transition Diagram and Test Generarion for Combinational Circuit Part [in Japanese]

HASEGAWA Tetsu , MIURA Kyoko , OHMAMEUDA Toshiaki , ITO Hideo

The Transactions of the Institute of Electronics,Information and Communication Engineers. 00083(00003), 339-347, 2000-03-25

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25

Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis

KAJIHARA Seiji , NISHIGAYA Rikiya , SUMIOKA Tetsuji , KINOSHITA Kozo

IEICE transactions on information and systems 78(7), 811-816, 1995-07-25

References (11)
26

A Single Bridging Fault Location Technique for CMOS Combinational Circuits

YAMAZAKI Koji , YAMADA Teruhiko

IEICE transactions on information and systems 78(7), 817-821, 1995-07-25

References (10)
27

A Study for Testability of Redundant Faults in Combinational Circuits Using Delay Effects

YU Xiangqiu , TAKAHASHI Hiroshi , TAKAMATSU Yuzo

IEICE transactions on information and systems 78(7), 822-829, 1995-07-25

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28

Very Fast Fault Simulation for Voltage Stuck-at Faults in Analog/Digital Mixed Circuit

TESHIMA Shigeharu , CHUJO Naoya , TERASHIMA Ryuta

IEICE transactions on information and systems 78(7), 853-860, 1995-07-25

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29

Test Generation Algorithms (<Special Issue> VLSI-CAD and Artificial Intelligence) [in Japanese]

FUJIWARA Hideo , Hideo Fujiwara

Journal of the Japanese Society for Artificial Intelligence 8(2), 166-172, 1993-03-01

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30

Transistor Leakage Fault Diagnosis with I_<DDQ> and Logic Information

XIAOQING Wen , TAMAMOTO Hideo , KEWAL Saluja K. , KINOSHITA Kozo

IEICE transactions on information and systems 81(4), 372-381, 1998-04-25

References (17)
31

Transistor Leakage Fault Diagnosis for CMOS Circuits

WEN Xiaoqing , TAMAMOTO Hideo , SALUJA Kewal K. , KINOSHITA Kozo

IEICE transactions on information and systems 81(7), 697-705, 1998-07-25

References (18)
32

Test Generation for Sequential Circuits Based on Boolean Function Manipulation [in Japanese]

CHOI Hoyong , KOHARA Takashi , ISHIURA Nagisa , SHIRAKAWA Isao , MOTOHARA Akira

The Transactions of the Institute of Electronics,Information and Communication Engineers. A 76(6), 835-843, 1993-06-25

References (19) Cited by (7)
33

1 Multiple Primary Output Detection Test Pattern Generation [in Japanese]

NAKAZATO Daisuke , HOSOKAWA Toshinori , YAMAZAKI Koji , ISHIGURO Tsukasa , DATE Hiroshi

IEICE technical report. Dependable computing 104(664), 21-26, 2005-02-18

References (12) Cited by (1)
34

Diagnosis for Open Faults by Using Erroneous Path Tracing Based on Detecting/Un-detecting Information [in Japanese]

YAMAZAKI Koji , HIGAMI Yoshinobu , TAKAHASHI Hiroshi , TAKAMATSU Yuzo

IEICE technical report. Dependable computing 104(664), 81-86, 2005-02-18

References (12)
35

On generation of high-quality test patterns for transition faults [in Japanese]

MORISHIMA Shohei , YAMAMOTO Masahiro , KAJIHARA Seiji , WEN Xiaoqing , FUKUNAGA Masayasu , HATAYAMA Kazumi , AIKYO Takashi

IEICE technical report 106(528), 25-30, 2007-02-02

References (21)
36

Analysis of Effective Decision Nodes on Test Generation [in Japanese]

OMORI Yusho , HOSOKAWA Toshinori , YOSHIMURA Masayoshi , YAMAZAKI Kouji

IEICE technical report 106(528), 37-42, 2007-02-02

References (16)
37

On Efficient Identification and Preservation of Indirect Implications in Static Learning [in Japanese]

SARUWATARI Keitaro , KAJIHARA Seiji

IEICE technical report. Dependable computing 102(479), 25-28, 2002-11-21

References (13)
38

A Method for Fast Identification of Unnecessary-to-Test Paths for Delay Faults in Logic Circuits [in Japanese]

KAJIHARA Seiji , KINOSHITA Kozo , POMERANZ Irith , REDDY Sudhakar M.

The Transactions of the Institute of Electronics,Information and Communication Engineers. 00082(00007), 888-895, 1999-07

References (13)
39

An Enhanced Fault Model for High Defect Coverage [in Japanese]

SANG Junzhi , SHINOGI Tsuyoshi , TAKASE Haruhiko , KITA Hidehiko , HAYASHI Terumine

The Transactions of the Institute of Electronics,Information and Communication Engineers. 00082(00007), 897-905, 1999-07

References (11)
40

Test Generation of Combinational Circuits by the Hopfield [in Japanese]

HORITA Tadayoshi , TAKANAMI Itsuo , WATANABE Takahiro

The Transactions of the Institute of Electronics,Information and Communication Engineers. A 00078(00009), 1217-1220, 1995-09-25

References (7)
41

A Study for Identification of Redundant Faults in Combinational Circuits [in Japanese]

MINAMIYAMA Tetsuro , TAKAMATSU Yuzo

The Transactions of the Institute of Electronics,Information and Communication Engineers. 00081(00010), 1149-1156, 1998-10

References (20) Cited by (1)
42

Test Generation for Stuck-On Faults in Pass-Transistor Logic SPL and Its DFT Circuits [in Japanese]

SHINOGI Tsuyoshi , HAYASHI Terumine , TAKI Kazuo

The Transactions of the Institute of Electronics,Information and Communication Engineers. 00081(00003), 328-340, 1998-03

References (26)
43

Evolution of Fault Tolerance Techniques-From the Past to the Future [in Japanese]

TOHMA Yoshihiro

IPSJ Magazine 36(12), 1145-1154, 1995-12-15

IPSJ References (93) Cited by (1)

On the Acceleration of Test Generation Algorithms

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