SOCRATES : A highly efficient automatic test pattern generation system

SOCRATES : A highly efficient automatic test pattern generation system

- SCHULZ M. H.

Cited by (43)

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- SCHULZ M. H.

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IEEE Trans. CAD

IEEE Trans. CAD, 126-137, 1988

Cited by: 43

1

Concurrent Generation of lrredundant Combinational Circuits and Minimal Test Sets [in Japanese]

KAJIHARA Seiji , KINOSHITA Kozo

IPSJ Journal 36(6), 1495-1501, 1995-06-15

IPSJ References (19)
2

On Invaliant Implication Relataions for Removing Partial Circuits [in Japanese]

ICHIHARA Hideyuki , KAJIHARA Seiji , KINOSHITA Kozo

The Transactions of the Institute of Electronics,Information and Communication Engineers. 00079(00012), 1037-1045, 1996-12-25

IR References (14)
3

On Processing Order for Obtaining Implication Relations in Static Learning

ICHIHARA Hideyuki , KAJIHARA Seiji , KINOSHITA Kozo

IEICE TRANSACTIONS on Information and Systems 83(10), 1908-1911, 2000-10-25

IR References (6) Cited by (9)
4

On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume [in Japanese]

KAJIHARA Seiji , DOI Yasumi , LI Lei , CHAKRABARTY Krishnendu

Technical report of IEICE. ICD 103(478), 31-36, 2003-11-21

References (20)
5

On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume [in Japanese]

KAJIHARA Seiji , DOI Yasumi , LI Lei , CHAKRABARTY Krishnendu

Technical report of IEICE. VLD 103(476), 31-36, 2003-11-28

References (20)
6

On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume [in Japanese]

KAJIHARA Seiji , DOI Yasumi , LI Lei , CHAKRABARTY Krishnendu

情報処理学会研究報告. SLDM, [システムLSI設計技術] 112, 61-66, 2003-11-27

References (20)
7

Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation [in Japanese]

DOI Yasumi , KAJIHARA Seiji , 温暁青 , LI Lei , CHAKRABARTY Krishnendu

情報処理学会研究報告. SLDM, [システムLSI設計技術] 117, 173-178, 2004-12-02

References (23)
8

Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation [in Japanese]

DOI Yasumi , KAJIHARA Seiji , 温暁青 , LI Lei , CHAKRABARTY Krishnendu

Technical report of IEICE. ICD 104(480), 103-108, 2004-12-02

References (23)
9

Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation [in Japanese]

DOI Yasumi , KAJIHARA Seiji , 温暁青 , LI Lei , CHAKRABARTY Krishnendu

IEICE technical report. Dependable computing 103(482), 103-108, 2004-12-02

References (23)
10

Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation [in Japanese]

DOI Yasumi , KAJIHARA Seiji , 温暁青 , LI Lei , CHAKRABARTY Krishnendu

Technical report of IEICE. VLD 104(478), 103-108, 2004-12-02

References (23)
11

Test Generation for Acyclic Sequential Circuits using Combinational ATPG for Single Stuck-at Faults [in Japanese]

ICHIHARA Hideyuki , INOUE Tomoo , TAMURA Akio

Technical report of IEICE. ICD 100(474), 203-208, 2000-11-30

References (15)
12

SPIRIT : A High Robust Combinational Test Generation Algorithm

GIZDARSKI Emil , FUJIWARA Hideo

Technical report of IEICE. ICD 100(474), 209-214, 2000-11-30

References (23)
13

Efficient generation method of indirect implication on ATPG [in Japanese]

YOSHIMURA Masayoshi , KAJIHARA Seiji , MATSUNAGA Yusuke

情報処理学会研究報告. SLDM, [システムLSI設計技術] 125, 49-53, 2006-05-11

References (6)
14

On Identifying Don't-Care Inputs of Test Patterns for Logic Circuits [in Japanese]

MIYASE Kohei , KAJIHARA Seiji

情報処理学会研究報告. SLDM, [システムLSI設計技術] 103, 111-116, 2001-11-28

References (16)
15

Efficient and High Quality Test Using Deterministic Built-in Test [in Japanese]

HATAYAMA Kazumi , NAKAO Michinobu , KIYOSHIGE Yoshikazu , NATSUME Koichiro , SATO Yasuo , NAGUMO Takaharu

IEICE technical report. Component parts and materials 102(620), 13-18, 2003-01-23

References (32)
16

On Identifying Don't-Care Inputs of Test Patterns for Logic Circuits [in Japanese]

MIYASE Kohei , KAJIHARA Seiji

IEICE technical report. Computer systems 101(473), 79-84, 2001-11-22

References (16)
17

On Improvement of an ATPG based on Real-valued Logic Simulation [in Japanese]

SHINOGI Tsuyoshi , UCHIDA Tomoyuki , KITA Hidehiko , HAYASHI Terumine

Technical report of IEICE. VLD 95(306), 9-16, 1995-10-19

References (14)
18

On Invariant Implication Relations in Redundancy Removal for Combinational Circuits [in Japanese]

KAJIHARA Seiji , ICHIHARA Hideyuki , KINOSHITA Kozo

Technical report of IEICE. VLD 95(307), 23-29, 1995-10-20

References (12)
19

Test Generation for Acyclic Sequential Circuits using Combinational ATPG for Single Stuck-at Faults [in Japanese]

ICHIHARA Hideyuki , INOUE Tomoo , TAMURA Akio

Technical report of IEICE. VLD 100(473), 203-208, 2000-11-23

References (15) Cited by (2)
20

SPIRIT : A High Robust Combinational Test Generation Algorithm

GIZDARSKI Emil , FUJIWARA Hideo

Technical report of IEICE. VLD 100(473), 209-214, 2000-11-23

References (23)
21

Efficient and High Quality Test Using Deterministic Built-in Test [in Japanese]

HATAYAMA Kazumi , NAKAO Michinobu , KIYOSHIGE Yoshikazu , NATSUME Koichiro , SATO Yasuo , NAGUMO Takaharu

Technical report of IEICE. ICD 102(622), 13-18, 2003-01-23

References (32)
22

An n-Detection Test Generation Method to Increase Fault Sensitization Coverage [in Japanese]

HOSOKAWA Toshinori , YAMAZAKI Koji

The IEICE transactions on information and systems 90(6), 1474-1482, 2007-06-01

References (13) Cited by (8)
23

A Method for Forward Test Generation of Sequential Circuits [in Japanese]

TAKAMATSU Yuzo , OGAWA Taijiro , TAKAHASHI Hiroshi

The Transactions of the Institute of Electronics,Information and Communication Engineers. 75(9), 864-873, 1992-09-25

References (25) Cited by (1)
24

On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume [in Japanese]

KAJIHARA Seiji , DOI Yasumi , LI Lei , CHAKRABARTY Krishnendu

電子情報通信学会技術研究報告. DC, ディペンダブルコンピューティング : IEICE technical report 103(480), 31-36, 2003-11-21

References (20)
25

A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational Circuits [in Japanese]

SHINOGI Tsuyoshi , HAYASHI Terumine

Transactions of Information Processing Society of Japan 41(4), 944-951, 2000-04-15

IPSJ References (10)
26

Logic Optimization: Redundancy Addition and Removal Using Implication Relations

ICHIHARA Hideyuki , KINOSHITA Kozo

IEICE transactions on information and systems 81(7), 724-730, 1998-07-25

References (13)
27

Test Generation for Sequential Circuits Based on Boolean Function Manipulation [in Japanese]

CHOI Hoyong , KOHARA Takashi , ISHIURA Nagisa , SHIRAKAWA Isao , MOTOHARA Akira

The Transactions of the Institute of Electronics,Information and Communication Engineers. A 76(6), 835-843, 1993-06-25

References (19) Cited by (7)
28

A Method of Static Test Compaction Based on Don't Care Identification

Kohei Miyase , Seiji Kajihara , SudharkarM.Reddy

Transactions of Information Processing Society of Japan 43(5), 1290-1293, 2002-05-15

IPSJ References (9) Cited by (6)
29

Test Generation for Test Compression Based on Statistical Coding

ICHIHARA Hideyuki , OGAWA Atsuhiro , INOUE Tomoo , TAMURA Akio

IEICE TRANSACTIONS on Information and Systems 85(10), 1466-1473, 2002-10-01

IR References (11) Cited by (6)
30

Test Cost Reduction for Logic Circuits : Reduction of Test Data Volume and Test Application Time [in Japanese]

HIGAMI Yoshinobu , KAJIHARA Seiji , ICHIHARA Hideyuki , TAKAMATSU Yuzo

The Transactions of the Institute of Electronics,Information and Communication Engineers. 87(3), 291-307, 2004-03-01

IR References (103) Cited by (4)
31

A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG

ICHIHARA Hideyuki , INOUE Tomoo

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences 86(12), 3072-3078, 2003-12-01

IR References (11) Cited by (4)
32

1 Multiple Primary Output Detection Test Pattern Generation [in Japanese]

NAKAZATO Daisuke , HOSOKAWA Toshinori , YAMAZAKI Koji , ISHIGURO Tsukasa , DATE Hiroshi

IEICE technical report. Dependable computing 104(664), 21-26, 2005-02-18

References (12) Cited by (1)
33

Efficient generation method of indirect implication on ATPG [in Japanese]

YOSHIMURA Masayoshi , KAJIHARA Seiji , MATSUNAGA Yusuke

IEICE technical report 106(32), 19-23, 2006-05-05

References (6)
34

On generation of high-quality test patterns for transition faults [in Japanese]

MORISHIMA Shohei , YAMAMOTO Masahiro , KAJIHARA Seiji , WEN Xiaoqing , FUKUNAGA Masayasu , HATAYAMA Kazumi , AIKYO Takashi

IEICE technical report 106(528), 25-30, 2007-02-02

References (21)
35

Analysis of Effective Decision Nodes on Test Generation [in Japanese]

OMORI Yusho , HOSOKAWA Toshinori , YOSHIMURA Masayoshi , YAMAZAKI Kouji

IEICE technical report 106(528), 37-42, 2007-02-02

References (16)
36

On Acceleration of Fault Simulation Based on Double Detection [in Japanese]

MIYAZAKI Shinji , KAJIHARA Seiji

Technical report of IEICE. ICD 101(470), 43-48, 2001-11-22

References (9)
37

On Efficient Identification and Preservation of Indirect Implications in Static Learning [in Japanese]

SARUWATARI Keitaro , KAJIHARA Seiji

IEICE technical report. Dependable computing 102(479), 25-28, 2002-11-21

References (13)
38

A Sequential Test Generation Method and a Binding Method for Testability Using Behavioral Description [in Japanese]

INOUE Ryoichi , FUJIWARA Hiroaki , HOSOKAWA Toshinori , FUJIWARA Hideo

IEICE technical report 110(316), 143-148, 2010-11-22

References (16)
39

A Sequential Test Generation Method and a Binding Method for Testability Using Behavioral Description [in Japanese]

INOUE Ryoichi , FUJIWARA Hiroaki , HOSOKAWA Toshinori , FUJIWARA Hideo

IEICE technical report 110(317), 143-148, 2010-11-22

References (16)
40

A Method for Fast Identification of Unnecessary-to-Test Paths for Delay Faults in Logic Circuits [in Japanese]

KAJIHARA Seiji , KINOSHITA Kozo , POMERANZ Irith , REDDY Sudhakar M.

The Transactions of the Institute of Electronics,Information and Communication Engineers. 00082(00007), 888-895, 1999-07

References (13)
41

An Enhanced Fault Model for High Defect Coverage [in Japanese]

SANG Junzhi , SHINOGI Tsuyoshi , TAKASE Haruhiko , KITA Hidehiko , HAYASHI Terumine

The Transactions of the Institute of Electronics,Information and Communication Engineers. 00082(00007), 897-905, 1999-07

References (11)
42

Test Generation for Stuck-On Faults in Pass-Transistor Logic SPL and Its DFT Circuits [in Japanese]

SHINOGI Tsuyoshi , HAYASHI Terumine , TAKI Kazuo

The Transactions of the Institute of Electronics,Information and Communication Engineers. 00081(00003), 328-340, 1998-03

References (26)
43

On Test Pattern Selection with a Limited Number of Tests [in Japanese]

ICHIHARA Hideyuki , KAJIHARA Seiji , KINOSHITA Kozo

The Transactions of the Institute of Electronics,Information and Communication Engineers. 00082(00007), 861-868, 1999-07

IR References (7) Cited by (2)

SOCRATES : A highly efficient automatic test pattern generation system

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Cited by: 43

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