Author(s)
Journal
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- ACM Computing Surveys
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ACM Computing Surveys 24(3), 293-318, 1992
Cited by: 35
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1
- Fine-Grained Power Gating Based on the Controlling Value of Logic Elements
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CHEN Lei , HORIYAMA Takashi , NAKAMURA Yuichi , KIMURA Shinji
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 91(12), 3531-3538, 2008-12-01
J-STAGE References (13) Cited by (4)
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2
- Timing Verification of Sequential Logic Circuits Based on Controlled Multi-Clock Path Analysis
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NAKAMURA Kazuhiro , KIMURA Shinji , TAKAGI Kazuyoshi , WATANABE Katsumasa
IEICE Trans. on Fundamentals, A 81(12), 2515-2520, 1998-12-01
References (8) Cited by (6)
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3
- An Efficient Method for Verification of Reactive System Specifications in Temporal Logic [in Japanese]
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AOSHIMA Takenobu , YONEZAKI Naoki , Takenobu Aoshima , Naoki Yonezaki , 松下電器産業株式会社 , 東京工業大学 , Matsushita Electric Industrial Co. Ltd. , Tokyo Institute of Technology
Computer Software 20(3), 30-53, 2003-05-23
J-STAGE References (17)
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4
- State Enumeration Based on Propositional Satisfiability [in Japanese]
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NAKAMURA Kazuhiro , MARUOKA Shinji , KIMURA Shinji , WATANABE Katsumasa
IEICE technical report. Circuits and systems 100(118), 123-130, 2000-06-22
References (14)
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5
- State Enumeration Based on Propositional Satisfiability [in Japanese]
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NAKAMURA Kazuhiro , MARUOKA Shinji , KIMURA Shinji , WATANABE Katsumasa
Technical report of IEICE. DSP 100(122), 123-130, 2000-06-22
References (14)
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6
- A Query Language with Lazy Evaluation and its Applications to Collaborative Work Support
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IWAIHARA Mizuho
IPSJ SIG Notes 116(2), 437-444, 1998-07-09
References (10) Cited by (1)
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7
- Fine-Grained Power Gating Based on the Controlling Value of Logic Gates
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CHEN Lei , HORIYAMA Takashi , NAKAMURA Yuichi , KIMURA Shinji
情報処理学会研究報告. SLDM, [システムLSI設計技術] 135, 55-60, 2008-05-01
References (11)
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8
- Fine-Grained Power Gating Based on the Controlling Value of Logic Gates
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CHEN Lei , HORIYAMA Takashi , NAKAMURA Yuichi , KIMURA Shinji
IEICE technical report 108(23), 19-24, 2008-05-09
References (11)
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9
- Verification of asynchronous systems based on Petri Net unfoldings
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KONDRATYEV Alex
Technical report of IEICE. CST 96(57), 17-23, 1996-05-23
References (20) Cited by (3)
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10
- Processing Incomplete Information With Dynamic View Algebra [in Japanese]
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IWAIHARA Mizuho
IEICE technical report. Data engineering 99(117), 51-56, 2007-12-08
References (8)
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11
- The Worst Case Size of OBDD Graph Representations and Patricia BDDs
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IWAIHARA Mizuho
IEICE technical report. Theoretical foundations of Computing 95(127), 47-55, 1995-06-23
References (11)
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12
- Equivalence test of bounded width OBDD [in Japanese]
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ICHIMURA Masakazu , TAKENAGA Yasuhiko
Technical Report of IEICE 100(481), 9-15, 2000-11-27
References (8) Cited by (1)
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13
- Learnability of Ordered Binary Decision Diagrams
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HIRATA Kouichi , SHINOHARA Ayumi , MATSUMOTO Satoshi
IEICE technical report. Theoretical foundations of Computing 95(374), 37-44, 1995-11-17
References (13)
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14
- On the Hardness of Approximating the Minimum Consistent OBDD Problem
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HIRATA Kouichi , SHIMOZONO Shinichi , SHINOHARA Ayumi
IEICE technical report. Theoretical foundations of Computing 96(45), 39-48, 1996-05-17
References (16)
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15
- Parallel Dynamic Variable Ordering for BDD on Shared-memory Parallel Machines [in Japanese]
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KONISHI Kenzo , KISHIMOTO Satoru , TAKI Kazuo
IEICE technical report. Computer systems 96(231), 63-70, 1996-08-27
References (14)
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16
- Design Verification of Arithmetic Circuits Using Residue BDD's [in Japanese]
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KIMURA Shinji
Technical report of IEICE. VLD 95(171), 1-8, 1995-07-21
References (8)
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17
- Timing Analysis of Logic Circuits with Multiple Clock Operations [in Japanese]
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KIMURA Shinji , HIRAO Makoto , TAKAGI Kazuyoshi , WATANABE Katsumasa
Technical report of IEICE. VLD 96(201), 53-58, 1996-07-26
References (6) Cited by (2)
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18
- Waiting False Path Analysis of Sequential Logic Circuits [in Japanese]
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NAKAMURA Kazuhiro , KIMURA Shinji , TAKAGI Kazuyoshi , WATANABE Katsumasa
Technical report of IEICE. VLD 97(577), 71-78, 1998-03-06
References (6) Cited by (1)
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19
- Multi-Clock Path Analysis Based on Propositional Satisfiability [in Japanese]
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NAKAMURA Kazuhiro , MARUOKA Shinji , KIMURA Shinji , WATANABE Katsumasa
Technical report of IEICE. VLD 99(475), 55-62, 1999-11-27
References (16) Cited by (3)
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20
- State Enumeration Based on Propositional Satisfiability [in Japanese]
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NAKAMURA Kazuhiro , MARUOKA Shinji , KIMURA Shinji , WATANABE Katsumasa
Technical report of IEICE. VLD 100(120), 123-130, 2000-06-15
References (14)
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21
- CCTomato : CMOS Logic Cell Characterization Tool [in Japanese]
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YOSHITOMI Susumu , OGAWA Kimihiro , MORINAGA Seiya , KIMURA Shinji
Technical report of IEICE. VLD 102(476), 71-78, 2002-11-21
References (8)
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22
- Waiting False Path Analysis of Sequential Logic Circuits [in Japanese]
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NAKAMURA Kazuhiro , KIMURA Shinji , TAKAGI Kazuyoshi , WATANABE Katsumasa
Technical report of IEICE. ICD 97(579), 71-78, 1998-03-06
References (6)
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23
- Multi-Clock Path Analysis Based on Propositional Satisfiability [in Japanese]
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NAKAMURA Kazuhiro , MARUOKA Shinji , KIMURA Shinji , WATANABE Katsumasa
Technical report of IEICE. ICD 99(477), 55-62, 1999-11-27
References (16)
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24
- CCTomato : CMOS Logic Cell Characterization Tool [in Japanese]
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YOSHITOMI Susumu , OGAWA Kimihiro , MORINAGA Seiya , KIMURA Shinji
Technical report of IEICE. ICD 102(477), 71-78, 2002-11-21
References (8)
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25
- Automatic Clock Gating Generation through Power-optimal Control Signal Selection
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MAN Xin , HORIYAMA Takashi , KIMURA Shinji
情報処理学会研究報告. SLDM, [システムLSI設計技術] 145, A1-A6, 2010-05-19
References (15)
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26
- Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating
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MAN Xin , HORIYAMA Takashi , KIMURA Shinji
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 93(12), 2472-2480, 2010-12-01
J-STAGE References (16) Cited by (3)
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27
- Automatic Multi-Stage Clock Gating Optimization Using ILP Formulation
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MAN Xin , HORIYAMA Takashi , KIMURA Shinji
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 95(8), 1347-1358, 2012-08-01
J-STAGE References (11)
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28
- Implicit Representations of Graphs by OBDDs and Patricia BDDs
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IWAIHARA Mizuho , HIROFUJI Masanori
IEICE transactions on fundamentals of electronics, communications and computer sciences 79(7), 1068-1078, 1996-07-25
References (12)
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29
- Petrify: A Tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers
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CORTADELLA Jordi , KISHINEVSKY Michael , KONDRATYEV Alex , LAVAGNO Luciano , YAKOVLEV Alexandre
IEICE Trans. Information and Systems, D 80(3), 315-325, 1997-03-25
References (37) Cited by (32)
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30
- Multi-Cycle Path Detection Based on Propositional Satisfiability with CNF Simplification Using Adaptive Variable Insertion
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NAKAMURA Kazuhiro , MARUOKA Shinji , KIMURA Shinji , WATANABE Katsumasa
IEICE transactions on fundamentals of electronics, communications and computer sciences 83(12), 2600-2607, 2000-12-01
References (16)
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31
- Detection of Anomalies in Packet Filter Configurations
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YIN Yi , BHUVANESWARAN R. S. , KATAYAMA Yoshiaki , TAKAHASHI Naohisa
IEICE technical report 106(34), 13-18, 2006-05-04
References (13)
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32
- Detection of Anomalies in Packet Filter Configurations
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YIN Yi , BHUVANESWARAN R. S. , KATAYAMA Yoshiaki , TAKAHASHI Naohisa
情報処理学会研究報告. DSM, [分散システム/インターネット運用技術] 41, 13-18, 2006-05-11
References (13)
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33
- CCTomato : CMOS Logic Cell Characterization Tool [in Japanese]
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YOSHITOMI Susumu , OGAWA Kimihiro , MORINAGA Seiya , KIMURA Shinji
IEICE technical report. Dependable computing 102(479), 71-78, 2002-11-21
References (8)
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34
- Sharing of Clock Gating Modules under Multi-Stage Clock Gating Control
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MAN Xin , HORIYAMA Takashi , KIMURA Tomoo , KAI Koji , KIMURA Shinji
IEICE technical report 110(316), 185-190, 2010-11-22
References (8)
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35
- Sharing of Clock Gating Modules under Multi-Stage Clock Gating Control
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MAN Xin , HORIYAMA Takashi , KIMURA Tomoo , KAI Koji , KIMURA Shinji
IEICE technical report 110(317), 185-190, 2010-11-22
References (8)