A monolithic 156 Mb/s clock and data recovery PLL circuit using the sample-and-hold technique

• ISHIHARA N.

収録刊行物

• IEEE J. Solid-State Circuits

  IEEE J. Solid-State Circuits 29 1566-1571, 1995

詳細情報

• CRID: 1574231876441287040
• NII論文ID: 80008030905
• データソース種別:
  • CiNii Articles