Fast Identification of Untestable Delay Faults Using Implications

Author(s)

1

On Efficient Identification and Preservation of Indirect Implications in Static Learning [in Japanese]

SARUWATARI Keitaro , KAJIHARA Seiji

Technical report of IEICE. ICD 102(477), 25-28, 2002-11-21

References (13)
2

A Path Selection Method of Delay Test for Transistor Aging [in Japanese]

NODA Mitsumasa , KAJIHARA Seiji , SATO Yasuo , MIYASE Kohei , WEN Xiaoqing , MIURA Takaya

IEICE technical report 109(315), 167-172, 2009-11-25

References (22)
3

Evaluation of Delay Testing Based on Path Selection

FUKUNAGA Masayasu , KAJIHARA Seiji , TAKEOKA Sadami , YOSHIMURA Shinichi

IEICE transactions on fundamentals of electronics, communications and computer sciences 86(12), 3208-3210, 2003-12-01

References (12)
4

Test Compaction for Path Delay Faults in Deep Submicron LSIs [in Japanese]

KAJIHARA Seiji , FUKUNAGA Masayasu , WEN Xiaoqing , MAEDA Toshiyuki , HAMADA Shuji , SATO Yasuo

IEICE technical report. Dependable computing 104(664), 93-98, 2005-02-18

References (25)
5

On Efficient Identification and Preservation of Indirect Implications in Static Learning [in Japanese]

SARUWATARI Keitaro , KAJIHARA Seiji

IEICE technical report. Dependable computing 102(479), 25-28, 2002-11-21

References (13)