VHDL : hardware description and design
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書誌事項
VHDL : hardware description and design
Kluwer Academic Publishers, c1989
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注記
Bibliography: p. [293]
Includes index
内容説明・目次
内容説明
VHDL is a comprehensive language that allows a user to deal with design complexity. Design, and the data representing a design, are complex by the very nature of a modern digital system constructed from VLSI chips. VHDL is the first language to allow one to capture all the nuances of that complexity, and to effectively manage the data and the design process. As this book shows, VHDL is not by its nature a complex language. In 1980, the U. S. Government launched a very aggressive effort to advance the state-of-the-art in silicon technology. The objective was to significantly enhance operating performance and circuit density for Very Large Scale Integration (VLSI) silicon chips. The U. S. Government realized that in order for contractors to be able to work together to develop VLSI products, to document the resulting designs, to be able to reuse the designs in future products, and to efficiently upgrade existing designs, they needed a common communication medium for the design data. They wanted the design descriptions to be computer readable and executable. They also recognized that with the high densities envisioned for the U. S. Government's Very High Speed Integrated Circuit (VHSIC) chips and the large systems required in future procurements, a means of streamlining the design process and managing the large volumes of design data was required. Thus was born the concept of a standard hardware design and description language to solve all of these problems.
目次
1 - Introduction.- Why VHDL.- Terminology and Conventions.- 2 - A Model of Hardware.- A Model of Behavior.- A Model of Time.- A Model of Structure.- 3 - Basics.- Structure and Behavior.- Data Types and Objects.- Data Types.- Objects.- Hooking Constructs Together.- Interface Lists.- Association Lists.- Major VHDL Constructs.- Entity Declarations.- Architecture Bodies.- Subprograms.- Packages and Use Clauses.- Libraries.- Library Units and Order of Analysis.- Visibility of a Primary Unit and Libraries.- 4 - Data Types.- Literals.- Scalar Types.- Composite Types.- Aggregates and String Literals.- Referencing Elements of Composites.- Subtypes.- Attributes.- Predefined Operators.- 5 - Behavioral Description.- Process Statements.- The Wait Statement: Activation and Suspension.- Behavioral Modeling - Sequential View.- Declarations.- Sequential Assignment.- Signal Assignment.- Signal Drivers.- Delay in Signal Assignments.- Variable Assignment.- Sequential Control.- Conditional Control.- Iterative Control.- Other Sequential Statements.- The Assertion Statement.- Procedure Calls.- The Return Statement.- The Null Statement.- Behavioral Modeling - Concurrent View.- Concurrent Statements and Equivalent Processes.- Concurrent Signal Assignment.- Concurrent Assertion Statement.- Resolved Signals.- A Counter Element.- 6 - Structural Description.- Basic Features of Structural Description.- Ports in Entity Declarations.- Port Modes and Direction of Data Flow.- Ports in Component Declarations.- Component Instantiation Statements.- Example: A Simple ALU.- Example: A Decoder.- Example: Data Bus.- Regular Structures.- Generate Statements.- Generics.- Configuration Specifications.- Default Values and Unconnected Ports.- Default Values.- Unconnected Ports.- 7 - Large Scale Design.- Managing Shared Designs.- Design Libraries and their Implementation.- Predefined Design Libraries.- The Use of Libraries for Revision Management.- Visibility and the Analysis Context.- Name Visibility in VHDL.- Access to External VHDL Libraries.- Partitioning a Design.- Concurrent and Sequential Procedure Calls.- The Block Statement.- Component Instantiations and Blocks.- Sharing Data Within a Design.- Specifying a Design Configuration.- How Component Binding Occurs.- Type Incompatibilities in Component Binding.- Mixing Structure and Behavior.- 8 - A Complete Example.- The Traffic Light Controller.- Creating the Specification.- Defining the System Types.- Creating the Interface.- The Body of the Specification.- Creating a Test Bench.- Partitioning the Design.- Choosing a Type Representation.- Revising the Specification.- The First Partition.- The Second Partition.- Starting the Implementation.- Setting Up the PLA.- 9 - Advanced Features.- Overloading.- Access Types.- File Types and I/O.- User-Defined Attributes.- Signal-Related Attributes.- Aliases.- Association by Subelement.- Guarded Assignment Statements.- Disconnection Specifications.- Null Transactions.- 10 - VHDL in Use.- A Device Controller.- Setup and Hold Timing.- A Neural Net.- A Systolic Array Multiplier.- Summary.- Appendix A - Predefined Environment261.- Reserved Words.- Attributes.- Type and Subtype Attributes.- Array Attributes.- Signal-Valued Attributes.- Signal-Related Attributes.- Packages.- The Package STANDARD.- The Package TEXTIO.- >Appendix B - VHDL Syntax.- >Appendix C - Suggested Reading.- >Index.
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