Defect and fault tolerance in VLSI systems

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書誌事項

Defect and fault tolerance in VLSI systems

edited by Israel Koren ... [et al.]

Plenum Press, c1989-c1990

  • v. 1
  • v. 2

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注記

"Proceedings of the International Workshop on Defect and Fault Tolerance in VLSI Systems, held October 6-7, 1988, in Springfield, Massachusetts"--T.p. verso

Vol. 2 edited by C.H. Stapper ... [et al.]

Includes bibliographies and index

内容説明・目次

巻冊次

v. 1 ISBN 9780306432248

内容説明

This book contains an edited selection of papers presented at the International Workshop on Defect and Fault Tolerance in VLSI Systems held October 6-7, 1988 in Springfield, Massachusetts. Our thanks go to all the contributors and especially the members of the program committee for the difficult and time-consuming work involved in selecting the papers that were presented in the workshop and reviewing the papers included in this book. Thanks are also due to the IEEE Computer Society (in particular, the Technical Committee on Fault-Tolerant Computing and the Technical Committee on VLSI) and the University of Massachusetts at Amherst for sponsoring the workshop, and to the National Science Foundation for supporting (under grant number MIP-8803418) the keynote address and the distribution of this book to all workshop attendees. The objective of the workshop was to bring t. ogether researchers and practition- ers from both industry and academia in the field of defect tolerance and yield en- ha. ncement in VLSI to discuss their mutual interests in defect-tolerant architectures and models for integrated circuit defects, faults, and yield. Progress in this area was slowed down by the proprietary nature of yield-related data, and by the lack of appropriate forums for disseminating such information. The goal of this workshop was therefore to provide a forum for a dialogue and exchange of views. A follow-up workshop in October 1989, with C. H. Stapper from IBM and V. K. Jain from the University of South Florida as general co-chairmen, is being organized.

目次

1 Yield Models for Defect-Tolerant VLSI Circuits: A Review.- 2 Wafer Scale Revisited.- 3 Models for Defects and Yield.- Defects, Faults and Semiconductor Device Yield.- On the Probability of Fault Occurrence.- A New Yield Formula for Fault-Tolerant Large Area Devices.- 4 Defect-Tolerant Designs.- Defect Tolerant Interconnects for VLSI.- Combining Architecture and Algorithm for Yield Enhancement and Fault Tolerance.- Design of a Fault-Tolerant DRAM with New On-Chip ECC.- 5 Defect Monitoring and Yield Projection.- Measurement and Distribution of Faults on Defect Test Site Chips.- Process Development and Circuit Design Interactions in VLSI Yield Improvement.- Yield Projection Based on Electrical Fault Distribution and Critical Structure Analysis.- Yield Model for Yield Projection from Test Site.- 6 Testing and Testable Designs.- Test Methods for Wafer-Scale Integration.- Fault Diagnosis of Linear Processor Arrays.- Fault Diagnosis of Array Processors with Uniformly Distributed Faults.- 7 Defect- and Fault-Tolerant Processors.- Designing for High Yield: The NS32532 Microprocessor.- Defect Tolerance in a 16 Bit Microprocessor.- Design Techniques for a Self-Checking Self-Exercising Processor.- Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors.- 8 Defect- and Fault-Tolerant Memories.- Diagnosis and Repair of Large Memories: A Critical Review and Recent Results.- A Reconfigurable SRAM 4.5 MBit WSI Memory.- Block Alignment: A Method for Increasing the Yield of Memory Chips that are Partially Good.- Fault Tolerant Integrated Memory Design.- 9 Reconfigurable Arrays.- Probabilistic Analysis of Yield and Area Utilization of Reconfigurable Rectangular Processor Arrays.- Fabrication-Time and Run-Time Fault-Tolerant Array Processors Using Single-Track Switches.- An Efficient Restructuring Approach for Wafer Scale Processor Arrays.- Orthogonal Mapping: A Reconfiguration Strategy for Fault Tolerant VLSI/WSI 2-Dimensional Arrays.- A General Model for Fault Covering Problems in Reconfigurable Arrays.- 10 Fault-Tolerant Arrays.- Defect Tolerance in a Wafer Scale Array for Image Processing.- Distributed Fault-Tolerant Embedding of Binary Trees and Rings in Hypercubes.- On the Analysis and Design of Hierarchical Fault-Tolerant Processor Arrays.- Contributors.
巻冊次

v. 2 ISBN 9780306435317

内容説明

Higher circuit densities, increasingly more complex application ohjectives, and advanced packaging technologies have suhstantially increased the need to incorporate defect-tolerance and fault-tolerance in the design of VLSI and WSI systems. The goals of defect-tolerance and fault-tolerance are yield enhancement and improved reliahility. The emphasis on this area has resulted in a new field of interdisciplinary scientific research. I n fact, advanced methods of defect/fault control and tolerance are resulting in enhanced manufacturahility and productivity of integrated circuit chips, VI.SI systems, and wafer scale integrated circuits. In 1987, Dr. W. Moore organized an "International Workshop on Designing for Yield" at Oxford University. Edited papers of that workshop were published in reference [II. The participants in that workshop agreed that meetings of this type should he con tinued. preferahly on a yearly hasis. It was Dr. I. Koren who organized the "IEEE Inter national Workshop on Defect and Fault Tolerance in VLSI Systems" in Springfield Massachusetts the next year. Selected papers from that workshop were puhlished as the first volume of this series [21.

目次

1 Models for VLSI Manufacturing Yield.- Fault-Free or Fault-Tolerant VLSI Manufacturing.- Yield Models - Comparative Study.- 2 Models for Defects and Yield.- A Unified Approach to Yield Analysis of Defect Tolerant Circuits.- Systematic Extraction of Critical Areas From IC Layouts.- The Effect on Yield of Clustering and Radial Variations in Defect Density.- 3 Implementation of Wafer Scale Integration.- Practical Experiences in the Design of a Wafer Scale 2-D Array.- Yield Evaluation of a Soft-Configurable WSI Switch Network.- ASP Modules: WSI Building-Blocks for Cost-Effective Parallel Computing.- 4 Fault Tolerance.- Fault-Tolerant k-out-of-n Logic Unit Network With Minimum Interconnection.- Extended Duplex Fault Tolerant System With Integrated Control Flow Checking.- Experience in Functional Test and Fault Coverage in a Silicon Compiler.- 5 Array Processors.- APES: An Evaluation Environment of Fault-Tolerance Capabilities of Array Processors.- Comparison of Reconfiguration Schemes for Defect Tolerant Mesh Arrays.- An Integer Linear Programming Approach to General Fault Covering Problems.- Probabilistic Analysis of Memory Repair and Reconfiguration Heuristics.- Arithmetic-Based Diagnostics in VLSI Array Processors.- 6 New Approaches and Issues.- Yield Improvement Through X-RAY Lithography.- Reliability Analysis of Application-Specific Architectures.- Fault Tolerance in Analog VLSI: Case Study of a Focal Plane Processor.- 7 Yield and Manufacturing Defects.- Yield Model With Critical Geometry Analysis for Yield Projection from Test Sites on a Wafer Basis With Confidence Limits.- SRAM/TEG Yield Methodology.- A Fault Detection and Tolerance Tradeoff Evaluation Methodology for VLSI Systems.- 8 Designs for Wafer Scale Integration.- A Hypercube Design on WSI.- An Efficient Reconfiguration Scheme for WSI of Cube-Connected Cycles With Bounded Channel Width.- A Communication Scheme for Defect Tolerant Arrays.

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