Tutorial test generation for VLSI chips

Author(s)

• Agrawal, Vishwani D.
• Seth, Sharad C.

Bibliographic Information

Tutorial test generation for VLSI chips

[edited by] Vishwani D. Agrawal and Sharad C. Seth

IEEE Computer Society Press , Order from IEEE Computer Society, c1988

• : casebound
• : microfiche

Other Title

Test generation for VLSI chips

Note

A collection of reprints of articles originally published from 1967 to 1988

Includes bibliographies

"Computer Society order number 786."

IEEE catalog number EH0278-2."

Description and Table of Contents

Description

Reprints of papers taken from 18 different journals, published between 1967 and 1987. They give a comprehensive overview of very large-scale integration testing. No significant prior experience in testing is assumed. Concepts and current practices are emphasized. Chapters are preceded by a tutorial.

by "Nielsen BookData"

Details

• NCID: BA07449360
• ISBN:
  • 081868786X
  • 0818647868
• LCCN: 88061362
• Country Code: us
• Title Language Code: eng
• Text Language Code: eng
• Place of Publication: Washington, D.C.,Los Angeles, CA
• Pages/Volumes: x, 401 p.
• Size: 29 cm