Algorithmic and register-transfer level synthesis : the system architect's workbench

著者

• Thomas, D. E. (Donald E.)

書誌事項

Algorithmic and register-transfer level synthesis : the system architect's workbench

by D.E. Thomas ... [et al.]

（The Kluwer international series in engineering and computer science, SECS 85 . VLSI, computer architecture, and digital signal processing）

Kluwer Academic Publishers, c1990

注記

Includes bibliographical references

Includes index

詳細情報

• NII書誌ID(NCID): BA08020570
• ISBN:
  • 0792390539
• LCCN: 89028031
• 出版国コード: us
• タイトル言語コード: eng
• 本文言語コード: eng
• 出版地: Boston
• ページ数/冊数: ix, 305 p.
• 大きさ: 25 cm
• 分類:
  • LCC : TK7874
  • DC20 : 621.39/5
• 件名:
  • LCSH : Integrated circuits -- Design and construction
  • LCSH : Computer architecture
• 親書誌ID:
  • BA0004729X