Design & test techniques for VLSI & WSI circuits
著者
書誌事項
Design & test techniques for VLSI & WSI circuits
（IEE Computing series, 15）
Peter Peregrinus on behalf of the Institution of Electrical Engineers, c1989
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Design and test techniques for VLSI and WSI circuits
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内容説明・目次
内容説明
This book provides an up-to-date view of VLSI and WSI design and test methodologies, combining an introduction to the topics covered with an indication of current research directions and results. The coverage is thus suitable for undergraduates studying microelectronic systems design, for postgraduate researchers and for graduate engineers and managers seeking an overview or introduction to semi- and full-custom large-scale chip design. The contributions have been carefully chosen to take the reader from an introductory treatment of the gate array design route, very typically favoured by new entrants into the business of custom chip design, through a study of more ambitious design tools that allow the user to progress naturally to full-custom design. Having establihsed the style of design tools that are either in current use, or which are likely to set the future style of chip design packages, the book moves on to review the related fields of design-for-testability and fault tolerant VLSI design. The final section of the book deals with the concept of Wafer Scale Integration - WSI - which offers very exciting opportunities for devices of large system-scale complexities.
目次
- Part 1 Design methods for custom VLSI chips: gate-array technology and design
- CAD tools for full-custom design
- software tools in teaching ASIC design. Part 2 Test and fault-tolerance in VLSI design: design-for-test (DFT) techniques
- DFT and ATE systems in practice
- fault-tolerant design for VLSI. Part 3 Wafer-scale integration: an introduction to WSI
- WSI design techniques and applications of WSI.
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