Hierarchical modeling for VLSI circuit testing

Author(s)

• Bhattacharya, Debashis
• Hayes, John P. (John Patrick)

Bibliographic Information

Hierarchical modeling for VLSI circuit testing

by Debashis Bhattacharya, John P. Hayes

（The Kluwer international series in engineering and computer science, VLSI, computer architecture, and digital signal processing）

Kluwer Academic Publishers, c1990

Note

Includes bibliographical references (p. [149]-155)

Details

• NCID: BA09998982
• ISBN:
  • 079239058X
• LCCN: 89024726
• Country Code: us
• Title Language Code: eng
• Text Language Code: eng
• Place of Publication: Boston
• Pages/Volumes: x, 159 p.
• Size: 24 cm
• Classification:
  • LCC : TK7874
  • DC20 : 621.39/5/0287
• Subject Headings:
  • LCSH : Integrated circuits -- Very large scale integration -- Testing
  • LCSH : Integrated circuits -- Very large scale integration -- Computer simulation
• Parent Bibliography ID:
  • BA0004729X