Hierarchical modeling for VLSI circuit testing

著者

• Bhattacharya, Debashis
• Hayes, John P. (John Patrick)

書誌事項

Hierarchical modeling for VLSI circuit testing

by Debashis Bhattacharya, John P. Hayes

（The Kluwer international series in engineering and computer science, VLSI, computer architecture, and digital signal processing）

Kluwer Academic Publishers, c1990

注記

Includes bibliographical references (p. [149]-155)

詳細情報

• NII書誌ID(NCID): BA09998982
• ISBN:
  • 079239058X
• LCCN: 89024726
• 出版国コード: us
• タイトル言語コード: eng
• 本文言語コード: eng
• 出版地: Boston
• ページ数/冊数: x, 159 p.
• 大きさ: 24 cm
• 分類:
  • LCC : TK7874
  • DC20 : 621.39/5/0287
• 件名:
  • LCSH : Integrated circuits -- Very large scale integration -- Testing
  • LCSH : Integrated circuits -- Very large scale integration -- Computer simulation
• 親書誌ID:
  • BA0004729X