Formal VLSI specification and synthesis : Proceedings of the IFIP WG 10.2/WG 10.5 International Workshop on Applied Formal Methods for Correct VLSI Design
著者
書誌事項
Formal VLSI specification and synthesis : Proceedings of the IFIP WG 10.2/WG 10.5 International Workshop on Applied Formal Methods for Correct VLSI Design
（VLSI Design methods, v. 1）
North-Holland , Distributed for the U.S. and Canada, Elsevier Science Pub. Co., 1990
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注記
Includes bibliographical references
内容説明・目次
内容説明
Functional and behavioral verification of correctness forms the bottleneck in current VLSI design systems. For economical reasons, design of VLSI circuits must be completely validated before manufacturing. Current VLSI validation is mainly done through extensive simulation. The emerging alternative is based on formal design and verification methods that guarantee correctness. This book describes original work in all aspects of formal hardware design methods. Topics covered include high-level specification, hardware description languages, formal hardware verification methods, guided synthesis methods, correctness preserving transformations, use of theorem provers for verification, formal proof of correctness, MOS timing verification methods, design for verifiability, and practical experiences.
目次
Guided Synthesis Methods. Boyer-Moore Assisted Specification and Synthesis. Higher Order Logic Based Specification and Synthesis. Specification Formalisms. Formal Design of Regular VLSI Structures. Appendix: Formal Design Benchmark Example.
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