Superscalar microprocessor design
著者
書誌事項
Superscalar microprocessor design
（Prentice Hall series in innovative technology）
Prentice Hall, c1991
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注記
Bibliographical references: p. 273-278
Includes index
内容説明・目次
内容説明
Supercalar architectures represent current steps in the evolution of general-purpose microprocessors. Now, a single chip can incorporate techniques that were once applicable only to large-scale, scientific processors. "Superscalar Microprocessor Design" is a comprehensive investigation into the design of general-purpose superscalar microprocessors. Intended for engineers, computer scientists and graduate students with a strong background in computer architecture, this technical tutorial concentrates mostly on reduced-instruction-set (RISC) processors, but also deals with complex instruction-set (CISC) processors.
The book also shows how superscalar processors relate to other architectural organizations, highlighting the unique characteristics of general-purpose microprocessors and how these characteristics affect design decisions; explores implementation alternatives, using a superscalar model of the MIPS R2000 architecture; covers compiler optimizations, describing the basic techniques and algorithms used and examining hardware in the light of software optimizations; and summarizes the potential for technical and commericial development of superscalar microprocessors, enabling readers to assess the risks associated with different design levels.
目次
1. Beyond Pipelining, CISC, and RISC.
2. An Introduction to Superscalar Concepts.
3. Developing an Execution Model.
4. Instruction Fetching and Decoding.
5. The Role of Exception Recovery.
6. Register Dataflow.
7. Out-of-Order Instruction Execution.
8. Memory Dataflow.
9. Complexity and Controversy.
10. Basic Software Scheduling.
11. Software Scheduling Across Branches.
12. Evaluating Alternatives: A Perspective on Superscalar Microprocessors.
References.
「Nielsen BookData」 より
