Layout minimization of CMOS cells

著者

• Maziasz, Robert L.
• Hayes, John P. (John Patrick)

書誌事項

Layout minimization of CMOS cells

by Robert L. Maziasz and John P. Hayes

（The Kluwer international series in engineering and computer science, SECS 160 . VLSI, computer architecture and digital signal engineering）

Kluwer Academic Publishers, c1992

注記

Includes bibliographical references (p. 157-165) and index

詳細情報

• NII書誌ID(NCID): BA19173529
• ISBN:
  • 0792391829
• LCCN: 91034031
• 出版国コード: us
• タイトル言語コード: eng
• 本文言語コード: eng
• 出版地: Boston
• ページ数/冊数: xii, 169 p.
• 大きさ: 25 cm
• 分類:
  • LCC : TK7871.99.M44
  • DC20 : 621.381/52
• 件名:
  • LCSH : Metal oxide semiconductors, Complementary -- Design and construction -- Data processing
  • LCSH : Computer-aided design
• 親書誌ID:
  • BA0004729X