Layout minimization of CMOS cells

Author(s)

• Maziasz, Robert L.
• Hayes, John P. (John Patrick)

Bibliographic Information

Layout minimization of CMOS cells

by Robert L. Maziasz and John P. Hayes

（The Kluwer international series in engineering and computer science, SECS 160 . VLSI, computer architecture and digital signal engineering）

Kluwer Academic Publishers, c1992

Note

Includes bibliographical references (p. 157-165) and index

Details

• NCID: BA19173529
• ISBN:
  • 0792391829
• LCCN: 91034031
• Country Code: us
• Title Language Code: eng
• Text Language Code: eng
• Place of Publication: Boston
• Pages/Volumes: xii, 169 p.
• Size: 25 cm
• Classification:
  • LCC : TK7871.99.M44
  • DC20 : 621.381/52
• Subject Headings:
  • LCSH : Metal oxide semiconductors, Complementary -- Design and construction -- Data processing
  • LCSH : Computer-aided design
• Parent Bibliography ID:
  • BA0004729X