Matrix computations on systolic-type arrays
著者
書誌事項
Matrix computations on systolic-type arrays
（The Kluwer international series in engineering and computer science, SECS 174）
Kluwer Academic Publishers, c1992
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注記
Includes bibliographical references (p. 267-275) and index
内容説明・目次
内容説明
Matrix Computations on Systolic-Type Arrays provides a framework which permits a good understanding of the features and limitations of processor arrays for matrix algorithms. It describes the tradeoffs among the characteristics of these systems, such as internal storage and communication bandwidth, and the impact on overall performance and cost. A system which allows for the analysis of methods for the design/mapping of matrix algorithms is also presented. This method identifies stages in the design/mapping process and the capabilities required at each stage.
Matrix Computations on Systolic-Type Arrays provides a much needed description of the area of processor arrays for matrix algorithms and of the methods used to derive those arrays. The ideas developed here reduce the space of solutions in the design/mapping process by establishing clear criteria to select among possible options as well as by a-priori rejection of alternatives which are not adequate (but which are considered in other approaches). The end result is a method which is more specific than other techniques previously available (suitable for a class of matrix algorithms) but which is more systematic, better defined and more effective in reaching the desired objectives.
Matrix Computations on Systolic-Type Arrays will interest researchers and professionals who are looking for systematic mechanisms to implement matrix algorithms either as algorithm-specific structures or using specialized architectures. It provides tools that simplify the design/mapping process without introducing degradation, and that permit tradeoffs between performance/cost measures selected by the designer.
目次
List of Figures. List of Tables. 1. Introduction. 2. Systolic-Type Arrays for Matrix Algorithms. 3. Regularization of Matrix Algorithms. 4. Realization of Fixed-Size Arrays. 5. Partitioning by Cut-and-Pile. 6. Partitioned Realizations Using Coalescing. 7. A Linear Pseudo-systolic Array. 8. Mapping Matrix Algorithms. 9. Summary and Further Research.
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