Synthesis for control dominated circuits : selected papers from the IFIP WG10.2/WG10.5 workshops, Grenoble, France, April and September 1992
著者
書誌事項
Synthesis for control dominated circuits : selected papers from the IFIP WG10.2/WG10.5 workshops, Grenoble, France, April and September 1992
（IFIP transactions, A . Computer science and technology ; 22）
North-Holland, 1993
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注記
Includes bibliographical references
内容説明・目次
内容説明
The investigation of efficient synthesis methods for complex control dominated ASICs using library resources, including data-path generators, is explored in this book. The first chapter addresses the synthesis of complex controllers and includes some novel aspects, such as new models (tokenized model, petri net and so on), efficient use of ROM and PLA generators for ultra large microcoded controllers and extensions to communication finite state machines, including parallel and hierarchical controllers. The second chapter focuses on data-path generation and synthesis, including discussion of the respective advantages of standard cell based solutions versus dedicated bit sliced architectures and automatic synthesis methods dedicated to data-path. Synthesis methods of ASICs described at an RTL level and having as the target precisely circuits made up of a controller and a data-path are considered in the third chapter.
The fourth and last chapter focuses on layout synthesis for modules or library block generation, from the basic problem of the automatic layout generation of complex MOS cells, to the generation of regular modules (arithmetic blocks and PLA), to library characterization and design portability.
目次
- Part 1 FSM synthesis: RTL controller synthesis, C. Huang et al
- timing-driven state assignment for controller-datapath systems, S.C.-Y. Huang and W. Wolf
- tokenized state machine model for synthesis of sequential circuits into EPLDs and FPGAs, A. Coppola et al
- synthesis of large controllers using ROM or PLA generators, L. Gerbaux et al
- flag/condition handling and branch assignment for large microcoded controllers, A. Kifli et al
- the synthesis of a parallel controller from a petri net model, J. Pardey
- specification and synthesis of communicating finite state machines, H. Belhadj et al
- controller implementation by communicating asynchronous sequential circuits generated from a petri net specification of required behaviour, J. Beister and R. wollowski. Part 2 Data-path: pathway - a datapath layout assembler, A. Baron Cohen and M. Shechory
- FITPATH - a process-independent datapath compiler providing high density layout, L. Ben Ammar and A. Greiner
- generation of optimized datapaths - bit-slice versus standard cells, R. Leveugle and C. Safinia
- regular module generation or standard cells - two alternative implementations of a library of functional building blocks, E. Katsadas et al
- design of data-path module generators from algorithmic representations, V. Moshnyaga et al
- data-path synthesis as grammar inference, F. Mavaddat. Part 3 RTL synthesis: microarchitecture/microcode synthesis from VHDL, E.T. Kapuya and M.D. Edwards
- AMICAL - architectural synthesis based on VHDL, I. Park et al
- RTLOptimizA - from control data flow graph to logic circuit, Y. Wu and I. Dorrington
- implementations of IF-statements in the TODOS microarchitecture synthesis system, P. Marwedel
- data part optimizations in the CALLAS synthesis environment, J. Biesenack et al
- ASYL - a control driven RTL synthesis system using library blocks, A. Mignotte et al
- clocking scheme selection for circuits made up of a controller and a datapath, C. Safinia and R. Leveugle. Part 4 Module generation: optimization strategies in symbolic compaction, F. Curatelli et al
- a general and efficient mask pattern generator for non-series-parallel CMOS transistor network, H. Zhang and K. Asada
- logic synthesis for automatic layout, P Abouzeid et al
- MADMACS - an environment for the layout of regular arrays, E. Gautrin and L. Perraudeau
- module generation in an architectural synthesis environment, J.F.M. Theeuwen et al
- BADGE - a synthesis tool for customized arithmetic building blocks, A. Muenzer
- automatic layout synthesis of pipelined multipliers for systolic arrays, A.G. Jost et al
- floorplan optimized topological partitioning of programmed logic arrays, A.J.W.M. ten Berg
- timing model accuracy issues and automated library characterization, A. Martinez
- design library portability - a case study, B. Conq et al. Part 5 Invited paper: benchmarking and the art of synthesis tool comparison, D.D. Gajski and N.D. Dutt.
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