Design automation for timing-driven layout synthesis
Author(s)
Bibliographic Information
Design automation for timing-driven layout synthesis
（The Kluwer international series in engineering and computer science, SECS 198 . VLSI,
Kluwer Academic Publishers, c1993
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Note
Includes bibliographical references (p. 247-266) and index
Description and Table of Contents
Description
Moore's law [Noy77], which predicted that the number of devices in tegrated on a chip would be doubled every two years, was accurate for a number of years. Only recently has the level of integration be gun to slow down somewhat due to the physical limits of integration technology. Advances in silicon technology have allowed Ie design ers to integrate more than a few million transistors on a chip; even a whole system of moderate complexity can now be implemented on a single chip. To keep pace with the increasing complexity in very large scale integrated (VLSI) circuits, the productivity of chip designers would have to increase at the same rate as the level of integration. Without such an increase in productivity, the design of complex systems might not be achievable within a reasonable time-frame. The rapidly increasing complexity of VLSI circuits has made de- 1 2 INTRODUCTION sign automation an absolute necessity, since the required increase in productivity can only be accomplished with the use of sophisticated design tools. Such tools also enable designers to perform trade-off analyses of different logic implementations and to make well-informed design decisions.
Table of Contents
List of Figures. 1. Introduction. 2. Delay Estimation. 3. Transistor Sizing Algorithms: Existing Approaches. 4. A Convex Programming Approach to Transistor Sizing. 5. Global Routing Using Zero-One Integer Linear Programming. 6. Timing-Driven CMOS Layout Synthesis. Bibliography. Index.
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