Asynchronous design methodologies : proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March-2 April, 1993
著者
書誌事項
Asynchronous design methodologies : proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March-2 April, 1993
（IFIP transactions, A . Computer science and technology ; 28）
North-Holland, 1993
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注記
Includes bibliographical references and index
内容説明・目次
内容説明
This publication reflects the current state-of-the-art in asynchronous design, which is currently enjoying a world-wide resurgence of interest. The papers, contributed by a diverse selection of international specialists in the field, offer a balance of theory and engineering practice. They are organized into three sections with the themes: synthesis and modelling; theory and specification; and engineering practice. It is hoped that, with its broad ranging approaches to the subject, the book will serve as an accurate record of the state of development in 1993 of what may, in the future, be a commercially significant technology. Hopefully it will also, in the meantime, encourage further research by the computer/VLSI designers and postgraduate students of today.
目次
- Part 1 Organization, synthesis and modelling: VLSI programming of a modulo-N counter with constant response time and constant power, K. van Berkel
- linear test times for delay-insensitive circuits - a compilation strategy, M. Roncken and R. Saeijs
- self-timed architecture of a reduced instruction set computer, I. David, et al
- self-timed fully pipelined multipliers, O. Salomon and H. Klar. Part 2 Theory and specification: normal form in a delay-insensitive algebra, R. Broenboom, et al
- synthesis of asynchronous control circuits from symbolic signal transition graphs, A.V. Yakolev, et al
- hazard-free asynchronous circuit synthesis, M.L. Yu, and P.A. Subrahmanyam
- automated synthesis of asynchronous interface circuits, L. Lavagno and A. Sangiovanni-Vincentelli
- implementing a stack as a delay-insensitive circcuit, M.B. Josephs and J.T. Udding
- solving a mutual exclusion problem with the RGD arbiter, J.C. Ebergen, et al. Part 3 Engineering practice: asynchronous multipliers as combinational handshake circcuits, J. Haans, et al
- design of self-timed multipliers - a comparison, J. Sparso, et al
- a CMOS VLSI implementation of an asynchronous ALU, J.D. Garside
- automatic synthesis of fast compact asynchronous control circuits, A. Davis, et al
- characterization and evaluation of a complied asynchronous IC, K. van Berkel et al.
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