Logic synthesis
Author(s)
Bibliographic Information
Logic synthesis
(Computer engineering series)
McGraw-Hill, c1994
Available at 16 libraries
  Aomori
  Iwate
  Miyagi
  Akita
  Yamagata
  Fukushima
  Ibaraki
  Tochigi
  Gunma
  Saitama
  Chiba
  Tokyo
  Kanagawa
  Niigata
  Toyama
  Ishikawa
  Fukui
  Yamanashi
  Nagano
  Gifu
  Shizuoka
  Aichi
  Mie
  Shiga
  Kyoto
  Osaka
  Hyogo
  Nara
  Wakayama
  Tottori
  Shimane
  Okayama
  Hiroshima
  Yamaguchi
  Tokushima
  Kagawa
  Ehime
  Kochi
  Fukuoka
  Saga
  Nagasaki
  Kumamoto
  Oita
  Miyazaki
  Kagoshima
  Okinawa
  Korea
  China
  Thailand
  United Kingdom
  Germany
  Switzerland
  France
  Belgium
  Netherlands
  Sweden
  Norway
  United States of America
Note
Includes bibliographical references and index
Description and Table of Contents
Description
Logic synthesis enables VSLI designers to rapidly lay out the millions of transistors and interconnecting wires that form the circuitry on modern chips, without having to plot each individual logic circuit. This guide to logic synthesis techniques spotlights not only the synthesis of two-level, multi-level and combinational circuits, but also their testability.
Table of Contents
Introduction.Translation from HDL Descriptions.Two-Level Combinatorial Circuits.Synthesis of Two-Level Circuits.Testability of Two-Level Circuits.Multilevel Combinational Circuits.Synthesis of Multilevel Circuits.Delay of Multilevel Circuits.Testability of Multilevel Circuits.Ongoing Work and Future Directions.
by "Nielsen BookData"