Specification and validation methods
著者
書誌事項
Specification and validation methods
(International schools for computer scientists)
Clarendon Press, c1995
大学図書館所蔵 全11件
  青森
  岩手
  宮城
  秋田
  山形
  福島
  茨城
  栃木
  群馬
  埼玉
  千葉
  東京
  神奈川
  新潟
  富山
  石川
  福井
  山梨
  長野
  岐阜
  静岡
  愛知
  三重
  滋賀
  京都
  大阪
  兵庫
  奈良
  和歌山
  鳥取
  島根
  岡山
  広島
  山口
  徳島
  香川
  愛媛
  高知
  福岡
  佐賀
  長崎
  熊本
  大分
  宮崎
  鹿児島
  沖縄
  韓国
  中国
  タイ
  イギリス
  ドイツ
  スイス
  フランス
  ベルギー
  オランダ
  スウェーデン
  ノルウェー
  アメリカ
注記
Includes bibliographical references
内容説明・目次
内容説明
The book combines a high-level introduction to the state of the art with the development of new methods for specification and validation of computing systems. The methods are elaborated for challenging and characteristic applications, spanning from semantics of programming languages and their implementation (PROLOG,CLPC(R) and CLAM,C++) to architecture design (VHDL), including also parallel and distributed programs as well as protocols (Kermit for example). The eleven chapters are written in a self-contained way, each by a leading expert. The book is unique for two reasons: it combines a state-of-the-art survey with a systematic presentation of recent advances, based on new ideas and approaches; its themes range from software to hardware design and the proposed methods are applied to specification and validation of complex real-life computing systems. This book is intended for researchers and graduate students in computer science. Systems programmers.
目次
Introduction. 1.: Evolving algebras 1993. Lipari guide. 2.: Annotated bibliography on evolving algebras. 3.: Program verification and Prolog. 4.: CLAM-specifications for provably correct compilation of CLP(R) program. 5.: The semantics of the C++ programming language. 6.: Verification of parameterized programs VHDL-based system-level hardware design. 7.: The Bakery Algorithm: yet another specification and verification. 8.: Kermit: specification and verification. 9.: Group membership protocol: specification and verification. 10.: Specification and verification of VHDL-based system-level hardware design. 11.: Specification and verification of Gate-level VHDL models of synchronous and asynchronous circuits
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