VHDL modeling for digital design synthesis
著者
書誌事項
VHDL modeling for digital design synthesis
Kluwer Academic, c1995
大学図書館所蔵 件 / 全10件
-
該当する所蔵館はありません
- すべての絞り込み条件を解除する
注記
Bibliography: p. [323]-326
Includes index
内容説明・目次
内容説明
The purpose of this book is to introduce VHSIC Hardware Description Lan guage (VHDL) and its use for synthesis. VHDL is a hardware description language which provides a means of specifying a digital system over different levels of abstraction. It supports behavior specification during the early stages of a design process and structural specification during the later implementation stages. VHDL was originally introduced as a hardware description language that per mitted the simulation of digital designs. It is now increasingly used for design specifications that are given as the input to synthesis tools which translate the specifications into netlists from which the physical systems can be built. One problem with this use of VHDL is that not all of its constructs are useful in synthesis. The specification of delay in signal assignments does not have a clear meaning in synthesis, where delays have already been determined by the im plementationtechnolo~y. VHDL has data-structures such as files and pointers, useful for simulation purposes but not for actual synthesis. As a result synthe sis tools accept only subsets of VHDL. This book tries to cover the synthesis aspect of VHDL, while keeping the simulation-specifics to a minimum. This book is suitable for working professionals as well as for graduate or under graduate study. Readers can view this book as a way to get acquainted with VHDL and how it can be used in modeling of digital designs.
目次
List of figures. Preface. 1. Introduction. 2. Basic structures in VHDL. 3. Types, operators and expressions. 4. Sequential statements. 5. Concurrent statements. 6. Subprograms and packages. 7. Modeling at the structural level. 8. Modeling at the RT level. 9. Modeling at the FSMD level. 10. Modeling at the algorithmic level. 11. Memories. 12. VHDL synthesis. 13. Writing efficient VHDL descriptions. 14. Practicing designs. References. A. Reserved words. B. Standard library packages. Index.
「Nielsen BookData」 より