VHDL coding styles and methodologies
Author(s)
Bibliographic Information
VHDL coding styles and methodologies
Kluwer Academic Publishers, c1995
Available at 3 libraries
  Aomori
  Iwate
  Miyagi
  Akita
  Yamagata
  Fukushima
  Ibaraki
  Tochigi
  Gunma
  Saitama
  Chiba
  Tokyo
  Kanagawa
  Niigata
  Toyama
  Ishikawa
  Fukui
  Yamanashi
  Nagano
  Gifu
  Shizuoka
  Aichi
  Mie
  Shiga
  Kyoto
  Osaka
  Hyogo
  Nara
  Wakayama
  Tottori
  Shimane
  Okayama
  Hiroshima
  Yamaguchi
  Tokushima
  Kagawa
  Ehime
  Kochi
  Fukuoka
  Saga
  Nagasaki
  Kumamoto
  Oita
  Miyazaki
  Kagoshima
  Okinawa
  Korea
  China
  Thailand
  United Kingdom
  Germany
  Switzerland
  France
  Belgium
  Netherlands
  Sweden
  Norway
  United States of America
Note
Includes bibliographical references and index
Description and Table of Contents
Description
This text offers an in-depth study of the VHDL language rules, coding styles and methodologies. It distinguishes good from poor coding methodologies using a symbology notation along with a rationale for each guideline. The VHDL concepts, rules and styles are demonstrated using complete compilable and simulatable examples which are also supplied on the accompanying disk. The book offers practical applications of VHDL and techniques that are current in the industry. It explains how to apply the VHDL guidelines using several complete examples. The "learning by example" teaching approach along with an in-depth presentation of the language rules application methodology provides the necessary knowledge to create digital hardware designs and models that are readable, maintainable, predictable, and efficient. It is intended for both college students and design engineers, and provides a practical approach to learning VHDL.
Table of Contents
- 1. VHDL Overview and Concepts. 2. Basic Language Elements. 3. Control Structures. 4. Drivers. 5. VHDL Timing. 6. Elements of Entity/Architecture. 7. Subprograms. 8. Packages. 9. User Defined Attributes, Specifications, and Configurations. 10. Functional Models and Testbenches. 11. UART Project. 12. Vital. 13. Design for Synthesis. Appendices: VHDL'93 and VHDL'87 Syntax Summary
- Package Standard
- Package Textio
- Package STD_Logic_1164
- VHDL Preferred Attributes.
by "Nielsen BookData"