VHDL answers to frequently asked questions
著者
書誌事項
VHDL answers to frequently asked questions
Kluwer Academic, c1997
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注記
Includes bibliographical references and index
内容説明・目次
内容説明
This text is a follow-up to the author's book "VHDL Coding Styles and Methodologies", (ISBN 0-7923-9598-0). On completion of his first book, the author continued teaching VHDL and actively participated in the comp.lang.vhdl newsgroup. During his experiences, he was enlightened by the many interesting issues and questions relating to VHDL and synthesis. These pertained to: misinterpretations in the use of the language; methods for writing error-free, and simulation-efficient, code for testbench designs and for synthesis; and general principles and guidelines for design verification. As a result of this wealth of public knowledge contributed by a large VHDL community, the author decided to act as a facilitator of this information by collecting different classes of VHDL issues, and by elaborating on these topics through complex simulatable examples. This book is intended for those who are seeking an enhanced proficiency in VHDL.
This text: emphasizes application of VHDL for synthesis; uses complete examples to demonstrate problems and solutions; provides a disk that includes all the book examples and other useful reference VHDL material; uses easy to remember symbology notation to emphasize language rules, good and poor methodology and coding styles; identifies obsolete VHDL constructs that must be avoided; identifies synthesizable/non-synthesizable structures; and uses a question and answer format to clarify and emphasize the concerns of VHDL users.
目次
Language Elements. Arrays. Drivers. Subprograms. Packages. Models. Synthesis. Design Verification and Testbench. Potpourri. Appendices: A: VHDL'93 and VHDL'87 Syntax Summary. B: Package Standard. C: Package TEXTIO. D: Package STD_LOGIC_1164. E: Package STD_LOGIC_ARITH. F: VHDL Predefined Attributes.
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