VHDL for designers
著者
書誌事項
VHDL for designers
Prentice Hall, 1997
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注記
Includes bibliographical references and index
内容説明・目次
内容説明
The specific goal of VHDL for Designers is not only to teach VHDL but also to describe how to use VHDL when designing an electronic system with modern design tools. The synthesis tools Synopsys, Mentor Graphics and ViewLogic are used.
目次
Preface.
1. Introduction to VHDL Concurrent VHDL.
2. Sequential VHDL.
3. Libnrary.
4. Package and Subprograms.
5. Structural VHDL.
6. RAM and ROM.
7. Testbench.
8. State Machines.
9. RTL Synthesis.
10. Design Methodology.
11. Test Methodology
13. Common Design Errors in VHDL and How to Avoid them.
14. Design Examples and Design Tips.
15. Development Tools.
16. Behavioural Synthesis.
17. Laboratories.
18. Answers.
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