Digital logic and state machine design

著者

書誌事項

Digital logic and state machine design

David J. Comer

（The Oxford series in electrical and computer engineering）

Oxford University Press, c1995

3rd ed

大学図書館所蔵 件 / 全2件

この図書・雑誌をさがす

注記

Includes bibliographical references and index

内容説明・目次

内容説明

From one of the best known and successful authors in the field, this new edition provides concise, practical coverage of digital system design aimed at undergraduates. The primary goal of this book is to illustrate that sequential circuits can be designed using state machine techniques. These methods apply to sequential circuit design as efficiently as Boolean algebra and Karnaugh mapping methods apply to combinatorial design. Comer presents the techniques involved, then proceeds directly to designing digital systems - a task comprising producing the schematic or block diagram of a system based on a given set of specifications. The design serves as the basis for the construction of the actual hardware system. This new edition introduces state machines earlier than in previous editions, amd adds new chapters on programmable logic devices and computer organization.

目次

  • Introduction to Digital Systems
  • 1.1 Overview
  • 1.2 The Integrated Circuit
  • 1.3 Design and Analysis
  • 1. Binary Systems and Logic Circuits
  • 1.1 The Advantages of Binary
  • 1.2 Number Systems
  • 1.3 The Use of Binary in Digital Systems
  • 1.4 Logic Gates
  • 1.5 Logic Families
  • 2. Boolean Algebra and Mapping Methods
  • 2.1 Boolean Algebra
  • 2.2 Karnaugh Maps
  • 2.3 Variable-Entered Maps
  • 2.4 Realizing Logic Functions with Gates
  • 2.5 Combinational Design Examples
  • 3. Logic Function Realization with MSI Circuits
  • 3.1 Combinational Logic with Multiplexers and Decoders
  • 3.2 Standard Logic Functions with MSI Circuits
  • 3.3 Design Problem Using MSI Circuits
  • 4. Flip-Flops, Counters, and Registers
  • 4.1 The Bistable Multivibrator
  • 4.2 Flip-Flop Applications
  • 5. Introduction to State Machines
  • 5.1 The Need for State Machines
  • 5.2 The State Machine
  • 5.3 Basic Concepts in State Machine Analysis
  • 6. Synchronous State Machine Design
  • 6.1 Sequential Counters
  • 6.2 State Changes Referenced to Clock
  • 6.3 Number of State Flip-Flops
  • 6.4 Input Forming Logic
  • 6.5 Output Forming Logic
  • 6.6 Generation of a State Diagram from a Timing Chart
  • 6.7 Redundant States
  • 6.8 General State Machine Architecture
  • 7. Interfacing and Design of Synchronous Systems
  • 7.1 Mainly Synchronous Systems
  • 7.2 Top-Down Design
  • 7.3 Design Procedures
  • 7.4 Design Examples
  • 7.5 Micscellaneous Aspects of State Machine Design
  • 8. Programmable Logic Devices
  • 8.1 Introduction to Programmable Logic Devices
  • 8.2 Read-Only Memory
  • 8.3 Programmable Logic Arrays
  • 8.4 Programmable Array Logic or PAL(R)
  • 8.5 Combinational PLD-Based State Machines
  • 8.6 State Machines on a Chip
  • 9. Digital Computing
  • 9.1 The Digital Computer
  • 9.2 Binary Arithmetic
  • 9.3 Arithmetic Circuits
  • 9.4 Memory Circuits
  • 9.5 The Control Unit
  • 10. Asynchronous State Machines
  • 10.1 The Fundamental-Mode Model
  • 10.2 Problems of Asynchronous Circuits
  • 10.3 Basic Design Principles
  • 10.4 An Asynchronous Design Example
  • Appendix 1 Logic Families
  • Appendix 2 Pulse Generating Circuits
  • ANSWERS TO DRILL PROBLEMS
  • ANSWERS TO SELECTED PROBLEMS
  • INDEX

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