Top-down design of high-performance sigma-delta modulators
著者
書誌事項
Top-down design of high-performance sigma-delta modulators
（The Kluwer international series in engineering and computer science, SECS 480 . Analog circuits and signal processing）
Kluwer Academic Publishers, c1999
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注記
Includes bibliographical references (p. 261-274) and index
内容説明・目次
内容説明
The interest for :I:~ modulation-based NO converters has significantly increased in the last years. The reason for that is twofold. On the one hand, unlike other converters that need accurate building blocks to obtain high res olution, :I:~ converters show low sensitivity to the imperfections of their building blocks. This is achieved through extensive use of digital signal pro cessing - a desirable feature regarding the implementation of NO interfaces in mainstream CMOS technologies which are better suited for implementing fast, dense, digital circuits than accurate analog circuits. On the other hand, the number of applications with industrial interest has also grown. In fact, starting from the earliest in the audio band, today we can find :I:~ converters in a large variety of NO interfaces, ranging from instrumentation to commu nications. These advances have been supported by a number of research works that have lead to a considerably large amount of published papers and books cov ering different sub-topics: from purely theoretical aspects to architecture and circuit optimization. However, so much material is often difficultly digested by those unexperienced designers who have been committed to developing a :I:~ converter, mainly because there is a lack of methodology. In our view, a clear methodology is necessary in :I:~ modulator design because all related tasks are rather hard.
目次
1. Introduction. 2. Oversampling Sigma-Delta A/D Converters: Basic Concepts and State of the Art. 3. Modeling of Error Mechanisms in Sigma-Delta Modulators. 4. Behavioral Simulation of Sigma-Delta Modulators. 5. SDOPT+FRIDGE: Tools for the Automatic Design of Sigma-Delta Modulators. 6. Integrated Circuit Design (I): A 17-bit 40k Sample/s Fourth-Order Cascade Sigma-Delta Modulator. 7. Integrated Circuit Design (II): A 13-bit 2.2MSample/s Fourth-Order Cascade Multi-Bit Sigma-Delta Modulator. References. Appendix. Index.
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