Principles of verifiable RTL design : a functional coding style supporting verification processes in Verilog
著者
書誌事項
Principles of verifiable RTL design : a functional coding style supporting verification processes in Verilog
Kluwer Academic Publishers, c2000
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注記
Includes bibliographical references (p. [231]-238) and index
内容説明・目次
内容説明
Explaining how you can write Verilog to describe chip designs at the RT-level in a manner that co-operates with verification processes, this text focuses on how this co-operation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labour costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process.
目次
Preface. 1. Introduction. 2. The Verification Process. 3. RTL Methodology Basics. 4. RTL Logic Simulation. 5. RTL Formal Verification. 6. Verifiable RTL Style. 7. The Bad Stuff. 8. Verifiable RTL Tutorial. 9. Principles of Verifiable RTL Design. Bibliography. A Comparing Verilog Construct Performance. B Quick Reference. Index.
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