Principles of asynchronous circuit design : a systems perspective
著者
書誌事項
Principles of asynchronous circuit design : a systems perspective
（European low-power initiative for electronic system design）
Klwer Academic Publishers, c2001
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注記
Includes bibliographical references and index
内容説明・目次
内容説明
Principles of Asynchronous Circuit Design - A Systems Perspective addresses the need for an introductory text on asynchronous circuit design. Part I is an 8-chapter tutorial which addresses the most important issues for the beginner, including how to think about asynchronous systems. Part II is a 4-chapter introduction to Balsa, a freely-available synthesis system for asynchronous circuits which will enable the reader to get hands-on experience of designing high-level asynchronous systems. Part III offers a number of examples of state-of-the-art asynchronous systems to illustrate what can be built using asynchronous techniques. The examples range from a complete commercial smart card chip to complex microprocessors.
The objective in writing this book has been to enable industrial designers with a background in conventional (clocked) design to be able to understand asynchronous design sufficiently to assess what it has to offer and whether it might be advantageous in their next design task.
目次
- Preface. Part I: Asynchronous circuit design - A tutorial
- J. Sparso. 1: Introduction. 1.1. Why consider asynchronous circuits? 1.2. Aims and background. 1.3. Clocking versus handshaking. 1.4. Outline of Part I. 2: Fundamentals. 2.1. Handshake protocols. 2.2. The Muller C-element and the indication principle. 2.3. The Muller pipeline. 2.4. Circuit implementation styles. 2.5. Theory. 2.6. Test. 2.7. Summary. 3: Static data-flow structures. 3.1. Introduction. 3.2. Pipelines and rings. 3.3. Building blocks. 3.4. A simple example. 3.5. Simple applications of rings. 3.6. FOR, IF, and WHILE constructs. 3.7. A more complex example: GCD. 3.8. Pointers to additional examples. 3.9. Summary. 4: Performance. 4.1. Introduction. 4.2. A qualitative view of performance. 4.3. Quantifying performance. 4.4. Dependency graph analysis. 4.5. Summary. 5: Handshake circuit implementations. 5.1. The latch. 5.2. Fork, join, and merge. 5.3. Function blocks - The basics. 5.4. Bundled-data function blocks. 5.5. Dual-rail function blocks. 5.6. Hybrid function blocks. 5.7. MUX and DEMUX. 5.8. Mutual exclusion, arbitration and metastability. 5.9. Summary. 6: Speed-independent control circuits. 6.1. Introduction. 6.2. Signaltransition graphs. 6.3. The basic synthesis procedure. 6.4. Implementations using state-holding gates. 6.5. Initialization. 6.6. Summary of the synthesis process. 6.7. Petrify: A tool for synthesizing SI circuits from STGs. 6.8. Design examples using Petrify. 6.9. Summary. 7: Advanced 4-phase bundled-data protocols and circuits. 7.1. Channels and protocols. 7.2. Static type checking. 7.3. More advanced latch control circuits. 7.4. Summary. 8: High-level languages and tools. 8.1. Introduction. 8.2. Concurrency and message passing in CSP. 8.3. Tangram: program examples. 8.4. Tangram: syntax-directed compilation. 8.5. Martin's translation process. 8.6. Using VHDL for asynchronous design. 8.7. Summary. Appendix: The VHDL channel packages. Part II: Balsa - An Asynchronous Hardware Synthesis System
- D. Edwards, A. Bardsley. 9: An introduction to Balsa. 9.1. Overview. 9.2. Basic concepts. 9.3. Tool set and design flow. 9.4. Getting Started. 9.5. Ancillary Balsa Tools. 10: The Balsa Language. 10.1. Data Types. 10.2. Data Typing Issues. 10.3. Control flow and Commands. 10.4. Binary/unary operators. 10.5. Program structure. 10.6. Example Circuits. 10.7. Selecting Channels. 11: Building library components. 11.1. Parameterised descriptions.
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