Systematic design of CMOS switched-current bandpass sigma-delta modulators for digital communication chips
著者
書誌事項
Systematic design of CMOS switched-current bandpass sigma-delta modulators for digital communication chips
Kluwer Academic Publishers, c2002
大学図書館所蔵 全3件
注記
Includes bibliographical references and index
内容説明・目次
内容説明
This very detailed book discusses architectures, circuits and procedures for the optimum design of bandpass sigma-delta A/D interfaces for mixed-signal chips in standard CMOS technologies. It provides uniquely in-depth coverage of switched-current errors, which supports the design of high performance SI chips.
目次
List of Figures. List of Tables. Preface. Acknowledgments. Prologue. 1: Bandpass Sigma-Delta A/D Converters - Fundamentals and State-of-the-Art. 1.1. Introduction. 1.2. Analog-to-digital interfaces for digital radio receivers. 1.3. Analog-to-Digital Conversion: Fundamentals. 1.4. Oversampling SD Analog-to-Digital Converters. 1.5. Bandpass SD modulators. 1.6. Synthesis of bandpass SD modulator architectures. 1.7. Decimation for bandpass SD ADCs. 1.8. State-of-the-art bandpass SD ADCs. 2: Switched-Current Building Blocks for SD Modulators. 2.1. Introduction. 2.2. Principle of Operation: The Current Memory Cell. 2.3. SI Integrators. 2.4. SI Differentiators. 2.5. SI Resonators. 2.6. SI quantizers. 2.7. Current Mode 1-bit D/A Converters. 3: Mechanisms of Error in Switched-Current Circuits. 3.1. Introduction. 3.2. Finite output-input conductance ratio error. 3.3. Charge injection error. 3.4. Settling error. 3.5. Mismatch error. 3.6. Electrical noise. 3.7. Maximum signal range - Class AB memory cells. 3.8. Other mechanisms of error. 3.9. Design considerations for SI memory cells. 4: Non-Ideal Performance of Switched-Current Bandpass SD Modulators. 4.1. Introduction. 4.2. Ideal noise shaping in fourth-order bandpass SD modulators. 4.3. Impact of linear errors on the performance of SI integrators. 4.4. Impact of linear errors on the performance of SI resonators. 4.5. Non-ideal quantization noise shaping in fourth-order BPSDMs. 4.6. Cumulative influence of SI errors on the quantization noise shaping. 4.7. Harmonic distortion due to non-linear SI errors. 4.8. SNR degradation due to non-linear SI errors. 4.9. Thermal noise in bandpass SD modulators. 5: Behavioral Simulation of Switched-Current SD Modulators. 5.1. Introduction. 5.2. Simulation of SI circuits. 5.3. Behavioural modeling of SI integrators. 5.4. Behavioural Modeling of 1-bit Quantizers and D/A Converters. 5.5. SDSI: A MATLAB based behavioural simulator for SI SD modulators. 5.6. SDSI Application: Effect of SI errors on single-loop LP and BP SD modulators. 6: Practical IC Implementations. 6.1. Introduction. 6.2. Bandpass SD modulators for AM digital radio receivers. 6.3. Switched-current implementation. 6.4. A high frequency current mode buffer. 6.5. Practical design issues. 6.6. Experimental results. 6.7. Illustrating by measurements the performance degradation with SI errors. References. Appendix A: Distortion analysis of SI memory cells with nonstationary input signals using Volterra series. Appendix B: Effect of mismatch error on the performance of a memory cell with non-unity gain. Index.
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