International workshop on innovative architecture for future generation high-performance processors and systems

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Bibliographic Information

International workshop on innovative architecture for future generation high-performance processors and systems

editors, Alex Veidenbaum, Kazuki Joe ; sponsored by DARPA/ITO PAC/C Program

IEEE Computer Society, c2002

Other Title

Innovative architecture for future generation high-performance processors and systems

International workshop on innovative architecture for future generation high-performance processors and systems (IWIA 2002)

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IEEE Computer Society Press Order Number PR01635

Includes bibliographical references and index

"Jan, 2002 Hawaii"

Description and Table of Contents

Description

Gathers the 12 papers presented during the January 2002 workshop on high performance computing, with an emphasis on low power design and network processing. Among the topics are reducing power with an L0 instruction cache using history-based prediction, tight nonlinear loop timing estimation, multig

by "Nielsen BookData"

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