Testing of digital systems

著者

書誌事項

Testing of digital systems

N.K. Jha and S. Gupta

Cambridge University Press, 2003

大学図書館所蔵 件 / 8

この図書・雑誌をさがす

注記

Includes bibliographical references and index

内容説明・目次

内容説明

Device testing represents the single largest manufacturing expense in the semiconductor industry, costing over $40 billion a year. The most comprehensive and wide ranging book of its kind, Testing of Digital Systems covers everything you need to know about this vitally important subject. Starting right from the basics, the authors take the reader through automatic test pattern generation, design for testability and built-in self-test of digital circuits before moving on to more advanced topics such as IDDQ testing, functional testing, delay fault testing, memory testing, and fault diagnosis. The book includes detailed treatment of the latest techniques including test generation for various fault models, discussion of testing techniques at different levels of integrated circuit hierarchy and a chapter on system-on-a-chip test synthesis. Written for students and engineers, it is both an excellent senior/graduate level textbook and a valuable reference.

目次

  • 1. Introduction
  • 2. Fault models
  • 3. Combinational logic and fault simulation
  • 4. Test generation for combinational circuits
  • 5. Sequential ATPG
  • 6. IDDQ testing
  • 7. Functional testing
  • 8. Delay fault testing
  • 9. CMOS testing
  • 10. Fault diagnosis
  • 11. Design for testability
  • 12. Built-in self-test
  • 13. Synthesis for testability
  • 14. Memory testing
  • 15. High-level test synthesis
  • 16. System-on-a-chip testing
  • Index.

「Nielsen BookData」 より

詳細情報

  • NII書誌ID(NCID)
    BA63307307
  • ISBN
    • 0521773563
  • 出版国コード
    uk
  • タイトル言語コード
    eng
  • 本文言語コード
    eng
  • 出版地
    Cambridge
  • ページ数/冊数
    xvi, 1000 p.
  • 大きさ
    26 cm
  • 分類
  • 件名
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