Static and dynamic performance limitations for high speed D/A converters
著者
書誌事項
Static and dynamic performance limitations for high speed D/A converters
（The Kluwer international series in engineering and computer science, SECS 761）
Kluwer Academic, c2004
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注記
Includes bibliographical references (p. [211]-218)
内容説明・目次
内容説明
Static and Dynamic Performance Limitations for High Speed D/A Converters discusses the design and implementation of high speed current-steering CMOS digital-to-analog converters.
Starting from the definition of the basic specifications for a D/A converter, the elements determining the static and dynamic performance are identified. Different guidelines based on scientific derivations are suggested to optimize this performance. Furthermore, a new closed formula has been derived to account for the influence of the transistor mismatch on the achievable resolution of the current-steering D/A converter. To allow a thorough understanding of the dynamic behavior, a new factor has been introduced. Moreover, the frequency dependency of the output impedance introduces harmonic distortion components which can limit the maximum attainable spurious free dynamic range. Finally, the last part of the book gives an overview on different existing transistor mismatch models and the link with the static performance of the D/A converter.
目次
Abstract. List of Symbols and Abbreviations.
1: Introduction. 1.1. Introduction. 1.2. Outline of the Research Work.
2: The D/A Converter: Functionality and Specifications. 2.1. Introduction. 2.2. The Basic D/A Converter Function. 2.3. The Characteristics of an Ideal D/A Converter. 2.4. The Performance Specifications of a D/A Converter. 2.5. The D/A Converter Specifications as a Function of the Application. 2.6. Conclusions.
3: CMOS D/A Converter Architectures. 3.1. Introduction. 3.2. The Resistor D/A Converter. 3.3. The Capacitor D/A Converter. 3.4. The Current-Steering D/A Converter. 3.5. Conclusions.
4: Static Behaviour of Current Steering D/A Converters. 4.1. Introduction. 4.2. Modelling of the Random Errors. 4.3. Modelling of the Systematic Errors. 4.4. Conclusion.
5: Dynamic Behaviour of Current Steering D/A Converters. 5.1. Introduction. 5.2. Major Contibutors. 5.3. SFDR-Bandwidth Limitations. 5.4. SFDR-Bandwidth Optimised Implementations. 5.5. Conclusion.
6: A Design Methodology for High Performance CMOS Current Steering D/A Converters. 6.1. Introduction. 6.2. Determining the Level of Segmentation in a Current Steering D/A Converter. 6.3. Architectural Choice of the Thermometer Decoder. 6.4. Design of the Synchronised Switch Driver. 6.5. Dimensioning the Unit Current Cell. 6.6. Conclusion.
7: Realisations. 7.1. Introduction. 7.2. High Accuracy D/A Converters. 7.3. High Speed D/A Converters. 7.4. High Speed, High Accuracy D/A Converters. 7.5. Low Power, High Speed D/A Converters. 7.6. Overview of Realised DACs. 7.7. Comparison with Literature. 7.8. Conclusion.
8: Transistor Mismatch: Evolution and Relevance. 8.1. Introduction. 8.2. Model of Lakshmikumar. 8.3. Model of Pelgrom. 8.4. Other Models. 8.5. Mismatch Parameters for the 0.5 and the 0.4 m CMOS Technology. 8.6. Transistor Mismatch Dependency on its Geometry. 8.7. Influence of the Surroundings of the Transistors on the Mismatch Behaviour. 8.8. The CMOS Current Steering D/A Converter as a Test Structure for Transistor Mismatch Parameter Extraction. 8.9. Conclusion.
Appendix 1: Appendix 2: Bibliography.
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