SystemVerilog for design : a guide to using SystemVerilog for hardware design and modeling
著者
書誌事項
SystemVerilog for design : a guide to using SystemVerilog for hardware design and modeling
Kluwer Academic Publishers,, c2004
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注記
Includes index
内容説明・目次
内容説明
SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs. This book, "SystemVerilog for Design", addresses the first aspect of the SystemVerilog extensions to Verilog. Important modeling features are presented, such as two-state data types, enumerated types, user-defined types, structures, unions, and interfaces. Emphasis is placed on the proper usage of these enhancements for simulation and synthesis. A companion to this book, "SystemVerilog for Verification", covers the second aspect of SystemVerilog.
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