Speculative execution in high performance computer architectures

書誌事項

Speculative execution in high performance computer architectures

edited by David Kaeli and Pen-Chung Yew

(Chapman & Hall/CRC computer and information science series / series editor, Sartaj Sahni)

Chapman & Hall/CRC, c2005

  • hbk.

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注記

Includes bibliographical references and index

内容説明・目次

内容説明

Until now, there were few textbooks that focused on the dynamic subject of speculative execution, a topic that is crucial to the development of high performance computer architectures. Speculative Execution in High Performance Computer Architectures describes many recent advances in speculative execution techniques. It covers cutting-edge research projects, as well as numerous commercial implementations that demonstrate the value of this latency-hiding technique. The book begins with a review of control speculation techniques that use instruction cache prefetching, branch prediction and predication, and multi-path execution. It then examines dataflow speculation techniques including data cache prefetching, address value and data value speculation, pre-computation, and coherence speculation. This textbook also explores multithreaded approaches, emphasizing profile-guided speculation, speculative microarchitectures, and compiler techniques.

目次

Introduction. Instruction cache prefetching. Branch prediction. Trace caches. Branch predication. Multipath execution. Data cache prefetching. Address prediction. Data speculation. Instruction precomputation: Dynamically removing redundant computations using profiling. Profile-Based speculation. Compilation and speculation. Multithreading and speculation. Exploiting Load/Store parallelism via memory dependence prediction. Resource flow microarchitectures.

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詳細情報

  • NII書誌ID(NCID)
    BA75425810
  • ISBN
    • 1584884479
  • LCCN
    2005041310
  • 出版国コード
    us
  • タイトル言語コード
    eng
  • 本文言語コード
    eng
  • 出版地
    Boca Raton, FL
  • ページ数/冊数
    xv, 435 p.
  • 大きさ
    24 cm
  • 分類
  • 件名
  • 親書誌ID
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