Computer architecture : a quantitative approach
著者
書誌事項
Computer architecture : a quantitative approach
Morgan Kaufmann Pub., an imprint of Elsevier, 2007
4th ed
- : pbk
大学図書館所蔵 全46件
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注記
Includes bibliographical references and index
内容説明・目次
内容説明
The era of seemingly unlimited growth in processor performance is over: single chip architectures can no longer overcome the performance limitations imposed by the power they consume and the heat they generate. Today, Intel and other semiconductor firms are abandoning the single fast processor model in favor of multi-core microprocessors--chips that combine two or more processors in a single package. In the fourth edition of Computer Architecture, the authors focus on this historic shift, increasing their coverage of multiprocessors and exploring the most effective ways of achieving parallelism as the key to unlocking the power of multiple processor architectures. Additionally, the new edition has expanded and updated coverage of design topics beyond processor performance, including power, reliability, availability, and dependability.
目次
Main Text
Chapter 1: Fundamentals of Computer Design
Chapter 2: Instruction-level Parallelism and its Exploitation
Chapter 3: Advanced Techniques for Exploiting Instruction-level Parallelism and their Limits
Chapter 4: Multiprocessors and Thread-level Parallelism
Chapter 5: Memory Hierarchy Design
Chapter 6: Storage Systems
Appendix A: Pipelining: Basic and Intermediate
Concepts
Appendix B: Instruction Set Principles and Examples
Appendix C: Introduction to Memory Hierarchy
CD
Appendix D: Embedded Systems (contributor: Thomas M. Conte, North Carolina State University)
Appendix E: Interconnection Networks (contributor: Timothy M. Pinkston, USC and Jose Duato, Simula)
Appendix F: Vector Processors (contributor: Krste Asanovic, MIT)
Appendix G: Hardware and Software for VLIW and EPIC
Appendix H: Large-Scale Multiprocessors and Scientific Apps
Appendix I: Computer Arithmetic (contributor: David Goldberg, Xerox PARC)
Appendix J: Survey of Instruction Set Architectures
Appendix K: Historical Perspectives with References
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