SystemVerilog for verification : a guide to learning the testbench language features

著者

• Spear, Chris

書誌事項

SystemVerilog for verification : a guide to learning the testbench language features

Chris Spear

Springer Science+Business Media, c2006

注記

Includes bibliographical references (p. [295]-296) and index

内容説明・目次

内容説明

"SystemVerilog for Verification" provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. The authors explain methodology concepts for constructing testbenches that are modular and reusable. The book includes extensive coverage of the SystemVerilog 3.1a constructs such as classes, program blocks, randomization, assertions, and functional coverage. It also reviews SystemVerilog 3.0 topics such as interfaces and data types. For hardware engineers, the book has several chapters with detailed explanations of Object Oriented Programming based on years of teaching OOP to hundreds of students. For software engineers, there is a wealth of information on testbenches, multithreaded code, and interfacing to hardware designs. The reader only needs to know the Verilog 1995 standard.

目次

Verification guidelines.- Data types.- Procedural statements and routines.- Basic OOP.- Connecting the testbench and design.- Randomization.- Threads and interprocess communication.- Advanced OOP and guidelines.- Functional coverage.- Advanced interfaces.- References.- Index.

「Nielsen BookData」 より

詳細情報

• NII書誌ID(NCID): BA8199138X
• ISBN:
  • 0387270361
• LCCN: 2006926262
• 出版国コード: us
• タイトル言語コード: eng
• 本文言語コード: eng
• 出版地: New York, NY
• ページ数/冊数: xxxiv, 301 p.
• 大きさ: 25 cm
• 分類:
  • LCC : TK7885.7
  • DC22 : 621.39/2
• 件名:
  • LCSH : Verilog (Computer hardware description language)
  • LCSH : Integrated circuits -- Verification