Languages and compilers for parallel computing : 19th International Workshop, LCPC 2006, New Orleans, LA, USA, November 2-4, 2006 : revised papers
著者
書誌事項
Languages and compilers for parallel computing : 19th International Workshop, LCPC 2006, New Orleans, LA, USA, November 2-4, 2006 : revised papers
（Lecture notes in computer science, 4382）
Springer, c2007
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注記
Includes bibliographical references and author index
内容説明・目次
内容説明
This book constitutes the thoroughly refereed post-proceedings of the 19th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2006, held in New Orleans, LA, USA in November 2006.
The 24 revised full papers presented together with two keynote talks cover programming models, code generation, parallelism, compilation techniques, data structures, register allocation, and memory management.
目次
Keynote I.- Compilation Techniques for Partitioned Global Address Space Languages.- Session 1: Programming Models.- Can Transactions Enhance Parallel Programs?.- Design and Use of htalib - A Library for Hierarchically Tiled Arrays.- SP@CE - An SP-Based Programming Model for Consumer Electronics Streaming Applications.- Session 2: Code Generation.- Data Pipeline Optimization for Shared Memory Multiple-SIMD Architecture.- Dependence-Based Code Generation for a CELL Processor.- Expression and Loop Libraries for High-Performance Code Synthesis.- Applying Code Specialization to FFT Libraries for Integral Parameters.- Session 3: Parallelism.- A Characterization of Shared Data Access Patterns in UPC Programs.- Exploiting Speculative Thread-Level Parallelism in Data Compression Applications.- On Control Signals for Multi-Dimensional Time.- Keynote II.- The Berkeley View: A New Framework and a New Platform for Parallel Research.- Session 4: Compilation Techniques.- An Effective Heuristic for Simple Offset Assignment with Variable Coalescing.- Iterative Compilation with Kernel Exploration.- Quantifying Uncertainty in Points-To Relations.- Session 5: Data Structures.- Cache Behavior Modelling for Codes Involving Banded Matrices.- Tree-Traversal Orientation Analysis.- UTS: An Unbalanced Tree Search Benchmark.- Session 6: Register Allocation.- Copy Propagation Optimizations for VLIW DSP Processors with Distributed Register Files.- Optimal Bitwise Register Allocation Using Integer Linear Programming.- Register Allocation: What Does the NP-Completeness Proof of Chaitin et al. Really Prove? Or Revisiting Register Allocation: Why and How.- Session 7: Memory Management.- Custom Memory Allocation for Free.- Optimizing the Use of Static Buffers for DMA on a CELL Chip.- Runtime Address Space Computation for SDSM Systems.- A Static Heap Analysis for Shape and Connectivity: Unified Memory Analysis: The Base Framework.
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