SystemVerilog for design : a guide to using SystemVerilog for hardware design and modeling

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書誌事項

SystemVerilog for design : a guide to using SystemVerilog for hardware design and modeling

by Stuart Sutherland, Simon Davidmann, Peter Flake ; foreword by Phil Moorby

Springer, c2006

2nd ed.

  • : pbk.

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注記

Includes bibliographical references and index

内容説明・目次

内容説明

In its updated second edition, this book has been extensively revised on a chapter by chapter basis. The book accurately reflects the syntax and semantic changes to the SystemVerilog language standard, making it an essential reference for systems professionals who need the latest version information. In addition, the second edition features a new chapter explaining the SystemVerilog "packages", a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final syntax and rerun using the latest version of the Synopsys, Mentor, and Cadance tools.

目次

to SystemVerilog.- SystemVerilog Declaration Spaces.- SystemVerilog Literal Values and Built-in Data Types.- SystemVerilog User-Defined and Enumerated Types.- SystemVerilog Arrays, Structures and Unions.- SystemVerilog Procedural Blocks, Tasks and Functions.- SystemVerilog Procedural Statements.- Modeling Finite State Machines with SystemVerilog.- SystemVerilog Design Hierarchy.- SystemVerilog Interfaces.- A Complete Design Modeled with SystemVerilog.- Behavioral and Transaction Level Modeling.

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