{"@context":{"owl":"http://www.w3.org/2002/07/owl#","bibo":"http://purl.org/ontology/bibo/","foaf":"http://xmlns.com/foaf/0.1/","rdfs":"http://www.w3.org/2000/01/rdf-schema#","prism":"http://prismstandard.org/namespaces/basic/2.0/","cinii":"http://ci.nii.ac.jp/ns/1.0/","dc":"http://purl.org/dc/elements/1.1/","dcterms":"http://purl.org/dc/terms/"},"@id":"https://ci.nii.ac.jp/ncid/BA86520416.json","@graph":[{"@id":"https://ci.nii.ac.jp/ncid/BA86520416#entity","@type":"bibo:Book","foaf:isPrimaryTopicOf":{"@id":"https://ci.nii.ac.jp/ncid/BA86520416.json"},"dc:title":[{"@value":"Retargetable processor system integration into multi-processor system-on-chip platforms"}],"dc:creator":"Andreas Wieferink, Heinrich Meyr, Rainer Leupers","dc:publisher":[{"@value":"Springer"}],"dcterms:extent":"xiv, 162 p.","cinii:size":"25 cm","dc:language":"eng","dc:date":"2008","cinii:ncid":"BA86520416","cinii:ownerCount":"1","foaf:maker":[{"@type":"foaf:Person","foaf:name":[{"@value":"Wieferink, Andreas"}]},{"@id":"https://ci.nii.ac.jp/author/DA04520749#entity","@type":"foaf:Person","foaf:name":[{"@value":"Meyr, Heinrich"}]},{"@id":"https://ci.nii.ac.jp/author/DA12944649#entity","@type":"foaf:Person","foaf:name":[{"@value":"Leupers, Rainer"}]}],"bibo:owner":[{"@id":"https://ci.nii.ac.jp/library/FA002495","@type":"foaf:Organization","foaf:name":"名古屋大学 工学 図書室","rdfs:seeAlso":{"@id":"https://m-opac.nul.nagoya-u.ac.jp/iwjs0023opc/ufirdi.do?ufi_target=ctlsrh&ncid=BA86520416&initFlg=_RESULT_SET_NOTBIB"}}],"prism:publicationDate":["c2008"],"dc:subject":["DC22:004.35"],"foaf:topic":[{"@id":"https://ci.nii.ac.jp/books/search?q=Multiprocessors","dc:title":"Multiprocessors"},{"@id":"https://ci.nii.ac.jp/books/search?q=Systems+on+a+chip","dc:title":"Systems on a chip"}],"dcterms:hasPart":[{"@id":"urn:isbn:9781402085741"}]}]}