SAT-based scalable formal verification solutions
著者
書誌事項
SAT-based scalable formal verification solutions
（Series on Integrated Circuits and Systems）
Springer, c2007
大学図書館所蔵 件 / 全3件
-
該当する所蔵館はありません
- すべての絞り込み条件を解除する
注記
Includes bibliographical references and index
内容説明・目次
内容説明
This book provides an engineering insight into how to provide a scalable and robust verification solution with ever increasing design complexity and sizes. It describes SAT-based model checking approaches and gives engineering details on what makes model checking practical. The book brings together the various SAT-based scalable emerging technologies and techniques covered can be synergistically combined into a scalable solution.
目次
Design Verification Challenges.- Design Verification Challenges.- Background.- Basic Infrastructure.- Efficient Boolean Representation.- Hybrid DPLL-Style SAT Solver.- Falsification.- SAT-Based Bounded Model Checking.- Distributed SAT-Based BMC.- Efficient Memory Modeling in BMC.- BMC for Multi-Clock Systems.- Proof Methods.- Proof by Induction.- Unbounded Model Checking.- Abstraction/Refinement.- Proof-Based Iterative Abstraction.- Verification Procedure.- SAT-Based Verification Framework.- Synthesis for Verification.
「Nielsen BookData」 より
