Practical design verification
著者
書誌事項
Practical design verification
Cambridge University Press, 2009
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注記
Includes bibliographical references and index
内容説明・目次
内容説明
Improve design efficiency and reduce costs with this practical guide to formal and simulation-based functional verification. Giving you a theoretical and practical understanding of the key issues involved, expert authors including Wayne Wolf and Dan Gajski explain both formal techniques (model checking, equivalence checking) and simulation-based techniques (coverage metrics, test generation). You get insights into practical issues including hardware verification languages (HVLs) and system-level debugging. The foundations of formal and simulation-based techniques are covered too, as are more recent research advances including transaction-level modeling and assertion-based verification, plus the theoretical underpinnings of verification, including the use of decision diagrams and Boolean satisfiability (SAT).
目次
- 1. Model checking and equivalence checking M. Fujita
- 2. Transaction level system modeling D. Gajski and S. Abdi
- 3. Result checking, monitors and assertions H. Foster
- 4. System debugging strategies W. Wolf
- 5. Test generation and coverage metrics M. Sonza Reorda, G. Squillero and E. Sanchez
- 6. System C and Vera in a verification flow S. Verma and I. G. Harris
- 7. Decision diagrams for verification M. Ciesielski, D. K. Pradhan and A. M. Jabir
- 8. Boolean satisfiability and EDA applications J. Marques-Silva.
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