Low-power high-level synthesis for nanoscale CMOS circuits
著者
書誌事項
Low-power high-level synthesis for nanoscale CMOS circuits
Springer, c2008
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注記
Includes bibliographical references and index
内容説明・目次
内容説明
This self-contained book addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation.
目次
High-Level Synthesis Fundamentals.- Power Modeling and Estimation at Transistor and Logic Gate Levels.- Architectural Power Modeling and Estimation.- Power Reduction Fundamentals.- Energy or Average Power Reduction.- Peak Power Reduction.- Transient Power Reduction.- Leakage Power Reduction.- Conclusions and Future Direction.
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