Third Caltech Conference on very large scale integration
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書誌事項
Third Caltech Conference on very large scale integration
Springer, c1983
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注記
"California Institute of Technology"
Includes bibliographical references
内容説明・目次
内容説明
The papers in this book were presented at the Third Caltech Conference on Very Large Scale Integration, held March 21-23, 1983 in Pasadena, California. The conference was organized by the Computer Science Depart ment, California Institute of Technology, and was partly supported by the Caltech Silicon Structures Project. This conference focused on the role of systematic methodologies, theoretical models, and algorithms in all phases of the design, verification, and testing of very large scale integrated circuits. The need for such disciplines has arisen as a result of the rapid progress of integrated circuit technology over the past 10 years. This progress has been driven largely by the fabrica tion technology, providing the capability to manufacture very complex elec tronic systems reliably and at low cost. At this point the capability to manufac ture very large scale integrated circuits has exceeded our capability to develop new product designs quickly, reliably, and at a reasonable cost. As a result new designs are undertaken only if the production volume will be large enough to amortize high design costs, products first appear on the market well past their announced delivery date, and reference manuals must be amended to document design flaws. Recent research in universities and in private industry has created an emerg ing science of very large scale integration.
目次
Invited Papers.- Practical Experience with VLSI Methodology.- CAPRI: A Design Methodology and a Silicon Compiler for VLSI Circuits Specified by Algorithms.- Design of a High Performance VLSI Processor.- Fundamental Issues in the Electrical Design of VLSI Circuits.- Circuit Timing.- Crystal: A Timing Analyzer for nMOS VLSI Circuits.- TV: An nMOS Timing Analyzer.- Optimizing Synchronous Circuitry by Retiming.- Routing and Interconnection.- A New Channel Routing Algorithm.- River Routing: Methodology and Analysis.- Area and Delay Penalties in Restructurable Wafer-Scale Arrays.- Formal System Models.- Verification of VLSI Designs.- A Hierarchical Simulator Based on Formal Semantics.- Trace Theory and the Definition of Hierarchical Components.- Deriving Circuits from Programs.- System Building Blocks.- Self-Timed IC Design with PPL's.- A Self-Timed Static RAM.- Design of the PSC: A Programmable Systolic Chip.- Special-Purpose Chip Architectures.- The VLSI Design of a Reed-Solomon Encoder Using Berlekamp's Bit-Serial Multiplier Algorithm.- A VLSI Chess Legal Move Generator.- New VLSI Architectures with Reduced Hardware.- Silicon Compilation.- Dumbo, A Schematic-to-Layout Compiler.- Macrocell Design for Concurrent Signal Processing.- A Case Study of the F.I.R.S.T. Silicon Compiler.
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