Materials, processes, and reliability for advanced interconnects for micro- and nanoelectronics--2009 : symposium held April 14-17, 2009, San Francisco, California, U.S.A.

書誌事項

Materials, processes, and reliability for advanced interconnects for micro- and nanoelectronics--2009 : symposium held April 14-17, 2009, San Francisco, California, U.S.A.

editors: Martin Gall ... [et al.]

(Materials Research Society symposium proceedings, v. 1156)

Materials Research Society, c2009

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注記

"..., 'Materials, processes, and reliability for advanced interconnects for micro- and nanoelectronics--2009," held April 14-17 at the 2009 MRS Spring Meeting in San Francisco, California, ..."--Pref.

Includes bibliographical references and indexes

内容説明・目次

内容説明

Enabled by the development and introduction of new materials, the semiconductor industry continues to follow Moore's law into 32nm and 22nm technologies. Advanced interconnect structures require the use of porous dielectrics with further reduced k-values and even weaker mechanical properties, as well as much thinner metallization liners. In addition, the increasing resistivity of Cu at decreasing dimensions must be addressed in order to maintain the performance of continuously shrinking devices. To deal with these issues, and to maintain the reliability of the interconnects, innovations in materials, processes and architectures are needed. This book brings together researchers from around the world to exchange the latest advances in materials, processes, integration and reliability in advanced interconnects and packaging, and to discuss interconnects for emerging technologies. Papers from a joint session with Symposium F, Packaging, Chip-Package Interactions and Solder Materials Challenges, are also included and focus on 3D chip stacking and molecular electronics.

目次

  • Part I. Low-k Dielectrics I
  • Part II. Low-k Dielectrics II
  • Part III. Poster Session: Interconnects
  • Part IV. Metalization I
  • Part V. Metallization II
  • Part VI. Reliability
  • Part VII. Emerging Interconnect Technologies
  • Part VIII. Joint Session: Interconnect and Packaging
  • Author index
  • Subject index.

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詳細情報

  • NII書誌ID(NCID)
    BB02098776
  • ISBN
    • 9781605111292
  • 出版国コード
    us
  • タイトル言語コード
    eng
  • 本文言語コード
    eng
  • 出版地
    Warrendale, Pa.
  • ページ数/冊数
    xiii, 189 p.
  • 大きさ
    24 cm
  • 親書誌ID
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