Transactional memory

著者

書誌事項

Transactional memory

Tim Harris, James Larus, Ravi Rajwar

(Synthesis lectures on computer architecture, 11)

Morgan & Claypool, c2010

2nd ed.

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注記

Includes bibliographical references: p209-244

内容説明・目次

内容説明

The advent of multicore processors has renewed interest in the idea of incorporating transactions into the programming model used to write parallel programs. This approach, known as transactional memory, offers an alternative, and hopefully better, way to coordinate concurrent threads. The ACI (atomicity, consistency, isolation) properties of transactions provide a foundation to ensure that concurrent reads and writes of shared data do not produce inconsistent or incorrect results. At a higher level, a computation wrapped in a transaction executes atomically - either it completes successfully and commits its result in its entirety or it aborts. In addition, isolation ensures the transaction produces the same result as if no other transactions were executing concurrently. Although transactions are not a parallel programming panacea, they shift much of the burden of synchronizing and coordinating parallel computations from a programmer to a compiler, to a language runtime system, or to hardware. The challenge for the system implementers is to build an efficient transactional memory infrastructure. This book presents an overview of the state of the art in the design and implementation of transactional memory systems, as of early spring 2010.

目次

Introduction Basic Transactions Building on Basic Transactions Software Transactional Memory Hardware-Supported Transactional Memory Conclusions

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詳細情報

  • NII書誌ID(NCID)
    BB05535232
  • ISBN
    • 9781608452354
  • 出版国コード
    us
  • タイトル言語コード
    eng
  • 本文言語コード
    eng
  • 出版地
    [San Rafael, Calif.]
  • ページ数/冊数
    xiv, 247 p.
  • 大きさ
    24 cm
  • 親書誌ID
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