Power management of digital circuits in deep sub-micron CMOS technologies : with 127 figures
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Bibliographic Information
Power management of digital circuits in deep sub-micron CMOS technologies : with 127 figures
（Advanced microelectronics, 25）
Springer, c2010
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Note
Includes bibliographical references and index
Description and Table of Contents
Description
This book provides an in-depth overview of design and implementation of leakage reduction techniques. The focus is on applicability, technology dependencies, and scalability. The book mainly deals with circuit design but also addresses the interface between circuit and system level design on the one side and between circuit and physical design on the other side.
Table of Contents
Dedication. Preface. List of Symbols. 1. INTRODUCTION TO LOW-POWER DIGITAL INTEGRATED CIRCUIT DESIGN. 1.1 Transistor Scaling in the Context of Power Consumption and Performance. 1.1.1 Fundamental CMOS Scaling Strategies. 1.1.2 Leakage Currents in Modern MOS Transistors. 1.1.3 Transistor Scaling in the Deep Sub-Micron Regime. 1.2 Classic Low-Power Strategies. 1.3 Low-Power Strategies beyond the Quarter Micron Technology node. 2. LOGIC WITH MULTIPLE SUPPLY VOLTAGES. 2.1 Principle of Multiple Supply Voltages. 2.2 Power Saving Capability and Voltage Assignment. 2.2.1 Supply Voltage Assignment Algorithm. 2.3 Level Conversion in Multi-VDD Circuits. 2.3.1 Asynchronous Levelshifter Design. 2.3.2 Design of Level Shifter FlipFlops. 2.3.3 Level Conversion in Dynamic Circuits. 2.4 Dynamic Voltage Scaling (DVS). 3. LOGIC WITH MULTIPLE THRESHOLD VOLTAGES. 3.1 Principle of Multiple Threshold Voltages. 3.2 Concept of Leakage Effective GateWidth for Leakage Estimation. 3.3 Impact of Supply and Threshold Voltage Variability on Gate Delay. 3.4 Active Body Bias Strategies. 3.4.1 Reverse Body Bias Technique (RBB). 3.4.2 Forward Body Bias Technique (FBB). 4. FORCING OF TRANSISTOR STACKS. 4.1 Principle of Stack Forcing. 4.1.1 Impact of Gate and Junction Leakage. 4.2 Stack Forcing as Leakage Reduction Technique. 5. POWER GATING. 5.1 Principle of Power Gating. 5.2 Design Trade-Offs of Power Gating. 5.3 Basic Properties of Power Gating. 5.3.1 Implementation of the Power Switch Devices. 5.3.2 Stationary Active and Idle State. 5.3.3 Transient Behavior During Block Activation. 5.3.4 Interfaces of a Sleep Transistor Block. 5.3.5 System Aspects of Power Gating. 5.4 Embodiments of Power Gating. 5.4.1 Sleep Transistor within Standard Cells. 5.4.2 Shared Sleep Transistor. 5.4.3 Optimization of Gate Potential - Gate Boosting and Super Cut-Off. 5.4.4 ZigZag Super Cut-Off CMOS. 5.4.5 Selective Sleep Transistor Scheme. 5.5 Demonstrator Design and Measurement.5.5.1 16-bit Multiply-Accumulate Unit. 5.5.2 16-bit Finite Impulse Response Filter. 5.5.3 Comparison of Current Profiles of Differently Pipelined Circuits. 5.6 Sleep Transistor Design Task. 5.6.1 Optimum Total Channel Width. 5.6.2 Optimum Channel Length. 5.6.3 Distributed vs. Localized Switch Placing. 5.6.4 Impact of Virtual Rail Decoupling. 5.7 Minimum Idle Time. 5.7.1 Functional Measurement Strategy of Minimum Power-Down Time. 5.7.2 Estimation of the Minimum Power-Down Time. 5.7.3 Charge Recycling Scheme. 5.7.4 Principle of Charge Recycling Scheme. 5.7.5 Fractional Switch Activation. 5.8 Block Activation Strategies. 5.8.1 Single Cycle Block Activation. 5.8.2 Sequential Switch Activation. 5.8.3 Stepwise Overdrive Incrementation. 5.8.4 Quasi-Continuous Overdrive Incrementation. 5.8.5 Double Switch Scheme. 5.8.6 Clock Gating During Activation. 5.9 State Conservation in Power Switched Circuits. 5.9.1 Static State Retention Flipflops. 5.9.2 Summary of Static State Retention Approaches. 5.9.3 Dynamic State Retention FlipFlops. 5.9.4 Trade-off Between Propagation Delay and Retention Time in Dynamic State Retention Flipflops. 6. CONCLUSION. References.
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