{"@context":{"owl":"http://www.w3.org/2002/07/owl#","bibo":"http://purl.org/ontology/bibo/","foaf":"http://xmlns.com/foaf/0.1/","rdfs":"http://www.w3.org/2000/01/rdf-schema#","prism":"http://prismstandard.org/namespaces/basic/2.0/","cinii":"http://ci.nii.ac.jp/ns/1.0/","dc":"http://purl.org/dc/elements/1.1/","dcterms":"http://purl.org/dc/terms/"},"@id":"https://ci.nii.ac.jp/ncid/BB09028462.json","@graph":[{"@id":"https://ci.nii.ac.jp/ncid/BB09028462#entity","@type":"bibo:Book","foaf:isPrimaryTopicOf":{"@id":"https://ci.nii.ac.jp/ncid/BB09028462.json"},"dc:title":[{"@value":"VHDL for logic synthesis"}],"dc:creator":"Andrew Rushton","dc:publisher":[{"@value":"John Wiley"}],"dcterms:extent":"xvi, 466 p.","cinii:size":"25 cm","dc:language":"eng","dc:date":"2011","cinii:ncid":"BB09028462","prism:edition":"3rd ed.","cinii:ownerCount":"2","foaf:maker":[{"@id":"https://ci.nii.ac.jp/author/DA03822276#entity","@type":"foaf:Person","foaf:name":[{"@value":"Rushton, Andrew"}]}],"bibo:owner":[{"@id":"https://ci.nii.ac.jp/library/FA001492","@type":"foaf:Organization","foaf:name":"東北大学 電気通信研究所 図書室","rdfs:seeAlso":{"@id":"http://opac.library.tohoku.ac.jp/opac/opac_openurl/?ncid=BB09028462"}},{"@id":"https://ci.nii.ac.jp/library/FA002622","@type":"foaf:Organization","foaf:name":"京都大学 吉田南総合図書館","rdfs:seeAlso":{"@id":"https://kuline.kulib.kyoto-u.ac.jp/opac/opac_openurl/?ncid=BB09028462"}}],"prism:publicationDate":["c2011"],"cinii:note":["Includes bibliographical references and index"],"dc:subject":["LCC:TK7885.7","DC21:621.39/5"],"foaf:topic":[{"@id":"https://ci.nii.ac.jp/books/search?q=VHDL+%28Computer+hardware+description+language%29","dc:title":"VHDL (Computer hardware description language)"},{"@id":"https://ci.nii.ac.jp/books/search?q=Logic+design+--+Data+processing","dc:title":"Logic design -- Data processing"},{"@id":"https://ci.nii.ac.jp/books/search?q=Computer-aided+design","dc:title":"Computer-aided design"}],"dcterms:hasPart":[{"@id":"urn:isbn:9780470688472"}]}]}